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| (R) STV82x6 Multistandard TV Audio Processor and Digital Sound Demodulator DATASHEET SDO WS SCK BUS0 BUS1 SDA SCL HPD Headphone Detection IS Interface IC Interface IC Bus Expander Audio Processing Loudspeaker Audio Processing Multi-Standard Digital Stereo Demodulator FM, AM, A2 and NICAM Audio Stereo D/A Vol./ Bal. Gain Loudspeaker LSL LSR SW Subwoofer Headphone HPL HPR IRQ STV82x6 Interrupt Request Demodulation Stereo Flag ST Source Preprocessing Sound IF SIF AGC A/D Smart Volume Control, ST WideSurround, 5-band Equalizer and Loudness, Beeper and Subwoofer Output Digital Audio Matrix Low Noise Audio Mute 1Vrms Headphone Audio Processing Smart Volume Control, Bass/Treble and Beeper 0.5Vrms Stereo Flag Mono In MONOIN Audio Stereo D/A Vol./ Bal. Low Noise Audio Mute 1Vrms Input SCARTs AI2L AI2R 2Vrms Input Analog Audio Matrix Audio Matrixing Output Analog Audio Matrix Low Noise Audio Mute 2Vrms AO1L AO1R Low Noise Audio Mute 2Vrms Single Crystal Clock Generation Power Supply Management DC Regulators, Standby mode 2Vrms AO2L AO2R AI3L AI3R XTI XTO This device incorporates the SRS (Sound Retrieval System) under licence from SRS Labs, Inc. Subwoofer output with Volume Control and Programmable Bandwidth Spatial Sound Effects (ST WideSurround and Pseudo-Stereo) SRSa 3D Surround 3-to-2 Analog Stereo Audio I/Os (SCART compatible) with Audio Matrix Low-noise Audio Mutes and Switches IS Output to interface with Dolbya Pro Logica Decoder IC Bus-controlled Single and standard 27 MHz Crystal Oscillator Power supplies: 3.3 V Digital, 5 V or 8 V Analog Embedded 3.3 V Regulators Packages: SDIP56 or TQFP80 Key Features NICAM, AM, FM Mono and FM 2 Carrier Stereo Demodulators for all sound carriers between 4.5 and 7 MHz Mono input provided for optimum AM Demodulation performances Demodulation controlled by Automatic Standard Recognition System Sound IF AGC with wide range Overmodulation and Carrier Offset recovery Smart Volume Control 5-band Equalizer & Bass/Treble Control Automatic Loudness Control Loudspeaker and Headphone outputs with Volume/Balance Controls and Beeper May 2004 Revision 2.2 1/95 Output Scarts AI1L AI1R 2Vrms Audio Stereo A/D Audio Stereo D/A STV82x6 Table of Contents Chapter 1 1.1 1.2 1.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Overview .............................................................................................................................. 5 Typical Applications ......................................................................................................... 5 I/O Pin Description ............................................................................................................... 8 Chapter 2 2.1 2.2 Demodulator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Digital Demodulator ............................................................................................................ 10 System Clock ..................................................................................................................... 14 Chapter 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Audio Processor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Main Features .................................................................................................................... 15 Smart Volume Control (SVC) ............................................................................................. 16 ST WideSurround ............................................................................................................... 17 5-Band Audio Equalizer ..................................................................................................... 17 Bass/Treble Control ........................................................................................................... 17 Volume/Balance Control .................................................................................................... 18 Automatic Loudness Control .............................................................................................. 20 Subwoofer Control ............................................................................................................. 20 Beeper ................................................................................................................................ 20 SRSTM 3D Surround (STV8226/36 only) ............................................................................ 21 Chapter 4 4.1 4.2 Audio Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Input Audio Matrix .............................................................................................................. 24 Output Audio Matrix ........................................................................................................... 24 Chapter 5 5.1 5.2 5.3 5.4 Additional Controls and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Interrupt Request ............................................................................................................... 25 IC Bus Expander ............................................................................................................... 25 Stereo Flag ......................................................................................................................... 25 Headphone Detection ........................................................................................................ 25 Chapter 6 IS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2/95 STV82x6 Chapter 7 7.1 7.2 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Supply Voltages ................................................................................................................. 27 Standby Mode .................................................................................................................... 28 Chapter 8 8.1 8.2 IC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 IC Address and Protocol ................................................................................................... 29 STV82x6 Reset .................................................................................................................. 29 Chapter 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 IC Register Map ................................................................................................................ 31 STV82x6 General Control Registers .................................................................................. 35 Analog Block ...................................................................................................................... 37 Clocking ............................................................................................................................. 39 Demodulator ....................................................................................................................... 41 Demodulator Channel 1 ..................................................................................................... 44 Demodulator Channel 2 ..................................................................................................... 47 NICAM Registers ............................................................................................................... 53 Zweiton ............................................................................................................................... 54 Sound Preprocessing and Selection Registers .................................................................. 55 Automatic Standard Recognition ........................................................................................ 62 Smart Volume Control ........................................................................................................ 66 Surround ............................................................................................................................ 68 5- Band Equalizer ............................................................................................................... 70 Loudness/Bass & Treble .................................................................................................... 72 Volume/Balance Control Registers .................................................................................... 74 Subwoofer .......................................................................................................................... 77 Beeper ................................................................................................................................ 78 Chapter 10 Chapter 11 11.1 11.2 11.3 11.4 Input/Output Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Absolute Maximum Ratings .............................................................................................. 84 Thermal Data .................................................................................................................... 84 Supply ................................................................................................................................ 84 Crystal Recommendations ................................................................................................ 85 3/95 STV82x6 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 Analog Sound IF Signal Recommendations ..................................................................... 85 SIF to LS/HP/SCART Path Characteristics ....................................................................... 86 SCART to SCART Analog Path Characteristics ............................................................... 86 SCART to I2S Output Path (via ADC) Characteristics ...................................................... 87 MONOIN to ADC and I2S Output Path Characteristics .................................................... 87 I2S to LS/HP/SW Path Characteristics ............................................................................. 87 I2S to SCART Path Characteristics .................................................................................. 88 Loudspeaker and Headphone Volume Control Characteristics ........................................ 88 MUTE Performance ........................................................................................................... 88 Digital I/Os ......................................................................................................................... 88 IC Bus Interface .............................................................................................................. 89 Chapter 12 Chapter 13 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 4/95 STV82x6 General Description 1 1.1 General Description Overview The STV82x6 is composed of three main parts: 1. TV Sound Demodulator: provides all the necessary circuitry for the demodulation of audio transmissions of European and Asian terrestrial TV broadcasts. The various transmission standards are automatically detected and demodulated without user intervention. 2. Audio Processor: based on DSP technology, independently controls loudspeaker, subwoofer and headphone signals. It offers basic and advanced features, such as a ST WideSurround, Equalizer, Automatic Loudness and Smart Volume Control for television viewer comfort. The STV8226/36 versions can perform additionally the SRSa 3D Surround for stereo and mono signals. 3. Audio Matrix: 3 stereo and 1 mono external analog audio inputs to loudspeakers and headphone, with 2 stereo external analog audio outputs (SCART compatible). Table 1: STV82x6 Version List Feature STV8206 X X STV8216 X X X STV8226 X X STV8236 X X X AM-FM Mono Zweiton NICAM ST WideSurround SRSa 3D Surround X X X X X X Figure 1: Package Ordering Information SDIP56 Package Order Code: STV82x6D TQFP80 Package Order Code: STV82x6 (Tray) STV82x6T (Tape & Reel) 1.2 Typical Applications Figure 2: Typical Application (Low-cost Stereo TV) Cable and Terrestrial Analog TV Tuner STV82x6 TV Sound Demodulation and Audio Processing 5/95 General Description Figure 3: Typical Application with Sub-woofer and Headphone STV82x6 Cable and Terrestrial Analog TV Tuner STV82x6 TV Sound Demodulation and Audio Processing Woofer Figure 4: Typical Application Electrical Diagram for STV82x6 in SDIP56 package C8 C9 SIF 100pF L1 10uH R3 560 10nF +5V R2 22 IC1 Interupt request (to 1 10uF L2 10uH C7 C5 100nF 5 GNDIF MONOIN AO1L AO1R VDCC GNDC AI1L AI1R VMC1 VMC2 AI2L AI2R VDDA GNDAH AO2L AO2R VDDH VREFA AI3L AI3R BGAP LSL LSR SW STV82x6D WS ST SDO CKTST VDD2 GND2 GNDP VDDP XTO XTI GNDSP GND1 VDD1 MCK SYSCK RESET REG SDA SCL ADR HPD GNDSA HPR HPL 52 51 50 49 48 47 C72 46 R6 270 k 45 44 43 42 41 40 39 NC 38 NC 1 BC337-40 +5V C1 C11 MONO IN C12 AO1L 1uF 6 + AO1R C15 AI1L 1uF AI1R 9 + 10uF + C16 C14 100nF 10 11 10uF C4 100nF 12 13 2 1uF C2 AI2L 1uF AI2R 1uF + 14 15 1 C17 C18 + + 100nF 10uF C70 C37 C67 100nF 22pF + C3 +8V 16 R4 330 17 + + C21 C19 10uF +8V 18 19 C33 470nF 100nF 20 21 22 37 C69 35 3 34 33 32 31 30 2 29 3 +5V L6 10uH 23 24 25 10uF + 36 R5 100k 2 T1 + C52 C53 C29 + C30 26 27 10uF 100nF 10uF 100nF 28 C20 AO2L 1 ST8 C68 10uF C22 AO2R C23 AI3L 1uF AI3R 1uF C26 LSL 1uF LSR 1uF C28 SW 1uF + 10uF C73 + + C25 100nF + C24 10uF 220nF + + C27 + + C31 HPL 1uF HPR +C32 1uF + HPD 6/95 27MHz XT1 + 10uF + C13 + P) SIF VTOP VREFIF VDDIF IRQ BUS0 BUS1 SCK 56 55 54 53 I2C bus expander I2C bus expander I2S SCK I2S WS I2S SDO STEREO Ident C35 100nF C6 220nF 2 3 100nF 4 7 8 C71 10uF C36 100nF 22pF SDA SCL STV82x6 LS Center LS Left LS Right Subwoofer HP Left/LS surround Left HP Right/LS surround Right L17 L8 10H + C9 330F L18 C69 33nF 100H C68 33nF C67 33nF C66 33nF C65 33nF C64 33nF * +1.8V * L16 100H C10 100nF L15 100H * * L14 Headphone detection 100H 1 * L13 1 +3.3V SL1 100H 2 C63 3 Address select 10F C13 100nF C62 33nF + C78 100H * 100nF C12 3 + + SCL SDA C14 100nF +3.3V L2 10H 0 R13 220 C58 100nF + C77 10F C57 100nF 0 0 R11 + R19 R8 220 R9 C75 +8V 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 R1 470K Reset +3.3V + SPDIF IN R14 100nF 0 C76 10F L7 10H + C17 10F 0 TQFP80 C18 100nF C19 100nF IC1 STV82x6 / STV82x7 R18 C15 SDA SCL N/C N/C ADR HPD N/C GNDSA HPR HPL SW LSR LSL N/C BGAP N/C AI3R AI3L VREFA N/C C16 470nF 330pF + C74 330pF R10 330 +8V + SPDIF OUT + +3.3V + + C46 1F 10F + + +1.8V R7 R6 220 220 C73 C72 330pF 330pF C44 100nF + 1 +1.8V SL2 C21 2 C26 100nF C42 100nF C25 100nF + + 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 N/C REG RESET SYSCK MCK VDD1 GND1 N/C GNDSP N/C N/C XTI XTO VDDP GNDP GND2 VDD2 CKTST N/C N/C VDDH AO2R AO2L GNDAH VDDA AI2R AI2L VMC2 N/C VMC1 AI1R AI1L GNDC VDDC N/C N/C N/C N/C AO1R AO1L R5 220 330pF R4 220 330pF C71 + C43 10F 10H L3 +8V 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 + 3 C27 R2 270k 0 100nF R15 + SDO ST/SDI WS SCK BUS1 N/C N/C BUS0 IRQ N/C N/C N/C SIF VTOP VREFIF VDDIF GNDIF MONOIN N/C N/C XT1 27MHz CRYSTAL 1 +1.8V 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SL3 2 C22 C70 C37 + + + R16 C36 3 C33 L6 0 100nF + C23 47F C32 220nF C34 + 10H C79 47F L4 +3.3V 10H L5 +1.8V 10H C35 IRQ 100pF SIF 1.8V 560 10H C29 100nF L11 22nF R17 C30 100nF C31 100nF 0 R3 Note : components with * are only mandatory in case of DOLBY certification Figure 5: Typical Compatible Application Electrical Diagram for STV82x6 and STV82x7 in TQFP80 package General Description STV82x6 / STV82x7 compatible Application Electrical Diagram + + C61 1F C60 1F C59 47F L1 10H C56 10F C55 10F C53 1F C54 1F C52 100nF C51 10F C45 1F C41 10F R12 82 +8V C47 10F C48 10F C40 10F C39 10F C38 1F 1F 1F + + + + C8 1F C7 1F C6 1F C5 1F C4 1F C3 1F + Part L1 L2 L3 L4 L5,L6 L8 L13,L14 L15,L16 L17,L18 R2 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 C3 C9 C10,C13 C15,C18 C21,C22 C23 C27,C29 C30 C31 C41 C42 C43 C59 C63 C64,C65 C66,C67 C68,C69 C70,C71 C72,C73 C74,C75 C76,C77 C78 C79 SL2 SL3 with STV82x7 10H Not Connected 10H Not Connected 10H 10H 100H * 100H * 100H * Not Connected Not Connected 0 ohm Not Connected 0 ohm Not Connected Not Connected 0 ohm 0 ohm Not Connected 0 ohm 1 F 330 F 100 nF 100 nF 27 pF 47 F 100 nF 100 nF Not Connected Not Connected 100 nF 10 F 47 F 33 nF 33 nF 33 nF 33 nF 330 pF 330 pF 330 pF Not Connected Not Connected 47 F between 1-2 between 1-2 with STV82x6 Not Connected 10H Not Connected 10H Not Connected Not Connected strap strap strap 270K 330 Not Connected 82 Not Connected 0 ohm 0 ohm Not Connected Not Connected 0 ohm Not Connected Not Connected Not Connected Not Connected Not Connected 22 pF Not Connected Not Connected Not Connected 100 nF 10 F Not Connected Not Connected 10 F 100 nF Not Connected Not Connected Not Connected Not Connected Not Connected Not Connected 10 F 10 F 10 F between 2-3 between 2-3 SC3 IN Right SC3 IN Left SC2 OUT Right SC2 OUT Left SC2 IN Right SC2 IN Left C50 100nF C49 SC1 IN Right SC1 IN Left SC3 OUT Right SC3 OUT Left SC1 OUT Right SC1 OUT Left SC4 IN Right SC4 IN Left Mono IN BUS EXPANDER / BUS0 I2S DATA 2 / BUS1 I2S DATA 1 / SCK I2S DATA 0 / WS I2S LR CLK / SDI I2S SCLK / SDO I2S PCM CLK 7/95 General Description STV82x6 1.3 I/O Pin Description Legend / Abbreviations for Table 2: Type: AP DP I O OD B A = Analog Power Supply = Digital Power Supply = Input = Output = Open Drain = Bidirectional = Analog Table 2: Pin Description SDIP 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TQFP 80 73 74 75 76 77 78 79/80 1 2 3/4/5/6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Name SIF VTOP VREFIF VDDIF GNDIF MONOIN N/C AO1L AO1R N/C VDDC GNDC AI1L AI1R VMC1 N/C VMC2 AI2L AI2R VDDA GNDAH AO2L AO2R VDDH N/C VREFA AI3L AI3R N/C BGAP Type A A A AP AP A A A AP AP A A A Sound IF Input ADC V TOP Decoupling Pin Function AGC Voltage Reference Decoupling Pin 3.3 V Power Supply for IF AGC & ADC 0 V Power Supply for IF AGC & ADC Mono Input Not Used Left SCART1 Audio Output Right SCART1 Audio Output Not used 3.3 V Power Supply for Audio DAC/ADC 0 V Power Supply for DAC/ADC Left SCART1 Audio Input Right SCART1 Audio Input Switched VREF Decoupling Pin for Audio Converters (VMCP) Not used VREF Decoupling Pin for Audio Converters (VMC) Left SCART2 Audio Input Right SCART2 Audio Input 3.3 V Power Supply for Audio Buffers, Matrix & Bias 0 V Power Supply for Audio Buffers & SCART Left SCART2 Audio Output Right SCART2 Audio Output 8 V / 5 V Power Supply for SCART & Audio Buffers Not Used Voltage Reference for Audio Buffers Left SCART3 Audio Input Right SCART3 Audio Input Not Used Bandgap Voltage Source Decoupling A A A AP AP A A AP A A A A 8/95 STV82x6 Table 2: Pin Description (Continued) SDIP 56 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 - General Description TQFP 80 27 28 29 30 31 32 33 34 35 36 37/38 39 40 41 42 43 44 45 46 47 48 49 50/51 52 53 54 55 56 57 58 59/60 61 62 63 64 65 66/67 68 69 70 71 72 Name N/C LSL LSR SW HPL HPR GNDSA N/C HPD ADR N/C SCL SDA N/C REG RESET SYSCK MCK VDD1 GND1 N/C GNDSP N/C XTI XTO VDDP GNDP GND2 VDD2 CKTST N/C SDO ST/SDI WS SCK BUS1 N/C BUS0 IRQ N/C N/C N/C Type Not Used A A A A A AP B I OD OD A I B B DP DP AP I O AP AP DP DP I B B B B B B B Left Loudspeaker Output Right Loudspeaker Output Subwoofer Output Left Headphone Output Right Headphone Output Substrate Analog/Digital Shield Not Used Function Headphone Detection Input (Active Low) Hardware IC Chip Address Control Not Used IC Serial Clock IC Serial Data Not Used 5 V Power Regulator Control Hardware Reset (Active Low) System Clock Output IS Master Clock Output 3.3V Power Supply for Digital Core & IO Cells 0V Power Supply for Digital Core & IO Cells Not Used Substrate Analog/Digital Shield for Clock-PLL Not Used Crystal Oscillator Input Crystal Oscillator Output 3.3 V Power Supply for Analog PLL Clock 0 V Power Supply for Analog PLL Clock 0 V Power Supply for Digital Core, DSPs & IO Cells 3.3 V Power Supply for Digital Core, DSPs & IO Cells Must be Connected to 0 V Not Used IS Bus Data Output Stereo Detection Output / IS Bus Data Input IS Bus Word Select Output IS Bus Clock Output IC Bus Expander Output 1 Not Used IC Bus Expander Output 2 IC Status Read Request Not Used Not Used Not Used 9/95 Demodulator Block STV82x6 2 Demodulator Block Figure 6: Demodulator Block Diagram Channel 1 = Mono Left AM Demodulator DCO1+ Mixer CAROFFSET1(22h) Channel Filter FIR1 FM Demodulator AM AM/FM Mono (To Sound Preprocessing) FML SIF AGC Amp AUTO_STAT(54h) A/D AUTO_CTRL(50h) AUTO_SCKM(51h) AUTO_SCKST(52h) Channel Filter FIR2 CAROFFSET2(3Ah) AUTOSTD DEMOD_STAT(0Dh) ZWT_STAT(41h) NICAM_STAT(3Fh) Zweiton Decoder AGC Control AGCC(0Eh) AGCS(0Fh) FM Demodulator FM Stereo (To Sound Preprocessing) DCO2 + Mixer DQPSK Demodulator NICAM Decoder NICAML NICAMR (To Sound Preprocessing) Channel 2 = Stereo/Mono Right Note: Zweiton is the Dual (Two Tone) FM stereo or A2 system. 2.1 2.1.1 Digital Demodulator Sound IF Signal The Analog Sound Carrier IF is connected to STV82x6 via the SIF pin. Before Analog-to-Digital Conversion (ADC), an Automatic Gain Control (AGC) is performed to adjust the incoming IF signal to the full scale of the ADC. A preliminary video rejection is recommended to optimize conversion and demodulation performances. The AGC system provides a wide range of SIF input levels and is activated for all standards, except L/L'. In this particular case, the sound carrier is AM-modulated and an automatic level adjustment would only damage transmitted audio signal. A preset IC parameter is required to define the gain of the AGC used in Manual mode (Registers AGCC and AGCS). 2.1.2 Demodulation The demodulation system operates by default in Automatic mode. In this mode, the STV82x6 is able to identify and demodulate any TV sound standard including NICAM and A2 systems (see Table 2) without any external control via the IC interface. It consists of the two demodulation channels (Channel 1 = Mono Left and Channel 2 = Mono Right/Stereo) to simultaneously process two sound carriers in order to handle all transmission modes (stereo and up to three mono languages). The built-in Automatic Standard Recognition System (AUTOSTD) automatically programs the appropriate bits in the IC registers which are forced to Read-only mode for users (see Section 9.1). The programming is optimized for each standard to be identified and demodulated. 10/95 STV82x6 Demodulator Block Each mono and stereo standard can be removed (or added) from the List of Standards to be recognized by programming registers AUTO_SCKM and AUTO_SCKST, respectively. The identified standard is displayed in register AUTO_STAT and any change to standard is flagged to the host system via pin IRQ. This flag must be reset by re-programming the MSBs of register AUTO_CTRL while checking the detected standard status by reading registers AUTO_STAT, NICAM_STAT and ZWT_STAT. Moreover, the detection of Stereo mode during demodulation is also flagged in register AUTO_STAT and on output pin ST. Important: L/L' and D/K standards cannot be automatically processed because the same frequency is used for the MONO carrier. An exclusive L/DK selection must programmed in register AUTO_CTRL. This may be externally controlled by detecting the RF modulation sign, which is negative for all TV standards except L/L'. To recover out-of standard FM deviations or the Sound Carrier Frequency Offset, additional IC controls are provided without interfering with the Automatic Standard Recognition System (AUTOSTD). DK-NICAM Overmodulation Recovery: Four different FM deviation ranges can be selected (via register AUTO_CTRL) for the DK standard while the AUTOSTD system remains active. The maximum FM deviation is 500 kHz in DK Mono mode and 350 kHz in DK NICAM mode (limited by overlapping FM and NICAM spectrum values). The demodulated signal peak level (proportional to the FM deviation) is detected by the Peak Detector and written to registers PEAK_DET_STATL and PEAK_DET_STATR. This value is used to implement Automatic Overmodulation Detection via an external IC control. Important: Only the selection of the 50 kHz FM deviation standard is compatible with the other DKA2* standards (DK1, DK2 or DK3). These standards must be removed from the list of standards (registers AUTO_SCKM and AUTO_SCKST) when programming larger FM deviations reserved only for DK-NICAM standards. Table 3: Standards covered by the Automatic Standard Recognition System (AUTOSTD) Type Carrier 1 Carrier 2 Name (MHz) (MHz) FM/AM Deviation De-emphasis Min. 15 4.724 50 s 5.5 A2 6.0 FM/NICAM AM Mono L AM/NICAM FM Mono D/K FM/NICAM D/K1 D/K2 D/K3 FM 2 Carriers FM 2 Carriers FM 2 Carriers A2* 6.5 5.850 6.258 6.742 5.742 27 50 80 50 s 54.6875 J17 40 5.850 0.5 1.0 J17 50 s 40 6.552 5.850 5.742 27 50 80 J17 100 27 50 80 J17 50 s 50 s 100 40 54.6875 System Sound Type Typ. 27 Max. 50 75 s RollPilot off Frequency (%) (kHz) FM Mono M/N FM 2 Carriers FM Mono B/G FM/NICAM FM 2 Carriers FM Mono I A2+ 4.5 55.069 11/95 Demodulator Block STV82x6 Sound Carrier Frequency Offset Recovery: Both Mono and Stereo IF Carrier frequencies can be adjusted independently (registers CAROFFSET1 and CAROFFSET2) within a large range (up to 120 kHz for standard mono FM deviations) while the AUTOSTD system remains active. The frequency offset estimation is written in registers FM_DCL and FM_DCR (Mono Left / Channel 1 And Mono Right / Channel 2, respectively) and can be used to implement the Automatic Frequency Control (AFC) via an external IC control. If required, the AUTOSTD system can be disabled (Manual mode) and the user can control all registers including those only controlled by the AUTOSTD function when active. Manual mode is selected in registers RESET or AUTO_SCKM. 2.1.3 Sound Preprocessing and Selection The demodulated sound signal can be redirected to 4 different output audio channels: 1. Loudspeaker & Subwoofer, 2. Headphone, 3. SCART, 4. IS Interface. Each output channel can independently select the demodulator source, analog SCART or IS inputs using register CH_SEL. Figure 7: Sound Preprocessing and Selection Block Diagram Peak Detector De-emphasis NICAM (From Demodulator) NICAM De-emphasis NICAM Prescaler NICAM Dematrix Channel & Language Selection FM_DCL(42h) FM_DCR(43h) PRE_FM(44h) Demodulation Matrix FM/AM (From Demodulator) DC Removal FM FM Prescaler FM Dematrix Digital Audio Matrix SCART Matrix CH_MX(48h) IS Matrix CH_MX(48h) CH_SEL(49h) CH_LANG(4Ah) PEAK_DET_CTRL(4Bh) PEAK_DET_STATL(4Ch) PEAK_DET_STATR(4Dh) LS IN (To Loudspeaker Processing) HP IN (To Headphone Processing) PRE_NICAM(45h) AUDIO IN (From Input Analog Audio Matrix) SCART Prescaler AUDIO OUT (To Output Analog Audio Matrix) PRE_AUX(46h) IS IN IS Prescaler IS OUT (To IS Interface) PRE_AUX(46h) 12/95 STV82x6 Demodulator Block The level of the demodulated sound may require adjusting in order to compensate for the difference in levels between the multiple source (NICAM, FM or AM) and standard source (FM deviation wide range from 15 to 500 kHz) signals. The correct range for all level variations (+24 to -6 dB) is selected in registers PRE_FM and PRE_NICAM. The internal sound level of the various sources (FM/AM, NICAM and SCART) is read in registers PEAK_DET_CTRL, PEAK_DET_STATL and PEAK_DET_STATR before audio processing and can be used to implement Automatic Pre-scaling via an external IC interface. In Automatic mode, the STV82x6 selects and performs all appropriate de-emphasis, dematrixing, sound selection and mute functions according to the standard and transmission mode detected. Mono system: Mono audio signals received by an FM or AM carrier are demodulated. Left and right audio outputs are identical. Automatic mute is applied when the mono standard cannot be identified. A2 systems (or Zweiton): Transmission of mono, stereo or bilingual audio signals using 2 separate FM carriers + identification pilot. The pilot, transmitted by the second carrier, can be modulated by two different tones in order to define Stereo or Dual-Mono mode. If not modulated, only the mono signal is broadcast on the first carrier. Zweiton mode is read in register ZWT_STAT and described in Table 4. In the event of poor signal detection, the audio output is switched back to FM Mono mode (backup). In Dual Mono mode, the language (A on Channel 1, B on Channel 2) can be selected separately for each audio output channel (Loudspeaker, Headphone, SCART or IS) in register CH_LANG. Table 4: A2 System Transmission Modes System Mode German Zweiton Mono German Zweiton Stereo German Zweiton Dual Mono (CH1=A, CH2=B) Korean Zweiton Mono Korean Zweiton Stereo Korean Zweiton Dual Mono (CH1 = A, CH2 = B) Zweiton undefined ZWT-STAT [2:0] 100 110 101 100 110 101 0XX or 111 FM Dematrix L,R (L+R)/2,R L,R L,R (L+R)/2,(L-R)/2 L,R L,R FM De-emphasis 50 s 50 s 50 s CH_LANG [1:0] XX XX 01 10 Sound Selection FM Mono FM Stereo FM Mono A FM Mono B FM Mono FM Stereo FM Mono A FM Mono B FM Mono Sound Backup X FM Mono X Mute X FM Mono X Mute X 75 s 75 s 75 s XX XX 01 10 50 s XX Note: A2 and A2* standards are German Zweiton, while A2+ is Korean Zweiton. NICAM systems: Transmission of mono, stereo, bilingual or trilingual audio signals using a modulated-QPSK carrier and an FM/AM sound carrier backup. The digital QPSK modulation broadcasts either channel stereo, dual mono, mono + data or data only. The selected NICAM mode is read in register NICAM_STAT and described in Table 5. In the event of high bit-error rates, the audio output is automatically switched back to the reserve sound transmission (FM/AM Mono) or muted if there is no backup. In Dual Mono or Stereo mode with no backup, the language can be selected separately for each audio output channel (Loudspeaker, Headphone, SCART or IS) in register CH_LANG. 13/95 Demodulator Block STV82x6 Table 5: NICAM System Transmission Modes NICAM_STAT[ 4:1] 1000 1010 System Mode NICAM Stereo NICAM Dual Mono (CH1 = A, CH2 = B) NICAM Mono+Data (D1 = A, D2 = Data) NICAM Data NICAM Stereo (no backup) NICAM CH_LANG[1:0] De-emphasis J17 J17 10 XX 01 Sound Selection NICAM Stereo NICAM Mono A NICAM Mono B NICAM Mono A FM/AM Mono FM/AM Mono A NICAM Stereo FM/AM Mono A NICAM Mono B Sound Backup FM/AM Mono FM/AM Mono Mute FM/AM Mono X X Mute X Mute 1001 1011 0000 J17 J17 J17 XX XX 01 00 01 NICAM Dual Mono (no backup) (D1 = B, D2 = C) 0010 J17 10 11 NICAM Mono C FM/AM Mono A NICAM Mono B FM/AM Mono X Mute X NICAM Mono+Data (no backup) (D1 = B, D2 = Data) NICAM undefined (no backup) 01 0001 X1XX J17 10 J17 XX Note: D1 and D2 define the two channels encoded in the NICAM packet. 2.2 System Clock The System Clock integrates a low-jitter PLL clock and can be fully reprogrammed via registers PLL_DIV, PLL_MD, PLL_PEH and PLL_PEL. The default values are designed for a standard 27-MHz quartz crystal frequency, which is the recommended frequency for minimizing potential RF interference in the application. This sinusoidal clock frequency, and any harmonic products, remains outside the TV picture and sound IF (PIF/SIF) and Band-I RF passbands and has been selected in order to reduce the risk of potential interference to the TV IF and RF system. However, if required, the PLL clock can be re-programmed for an other quartz crystal frequency within a range between 23 and 30 MHz. Note: A change in the crystal frequency is compatible with other default IC programming values, including those of the built-in Automatic Standard Recognition System. 14/95 STV82x6 Audio Processor Block 3 3.1 Audio Processor Block Main Features The STV82x6 Audio Processor is based on a dedicated audio Digital Signal Processor (DSP) that performs basic and advanced audio post-processing for 4 different output audio channels. 3.1.1 Loudspeaker and Subwoofer Features Smart Volume Control (See Note 1) Spatial effects: -- Pseudo Stereo (for Mono source) -- ST WideSurround ("Movie" and "Music" modes for Stereo source) 5-band Equalizer Volume and Balance controls (See Note 4) Automatic Loudness control Subwoofer (See Note 4) Beeper (See Note 3) Additionally on STV8226/36 only: SRSa 3D Mono signal processing SRSa 3D Stereo signal processing 3.1.2 Headphone (See Note 2) Smart Volume Control (See Note 1) Bass and Treble controls Volume and Balance controls Beeper (See Note 3) Note: 1 The Smart Volume Control can be used in either the loudspeaker or headphone path, but not both at the same time. 2 The headphone is forced into Mono mode when the subwoofer is active. 3 The beeper is common for both the loudspeaker and the headphone. 4 The Auto-mute function is activated when a headphone plug is detected. 5 All audio postprocessing can be disabled. 3.1.3 SCART 1 and 2 Outputs No audio post-processing 3.1.4 IS Output No audio post-processing 15/95 Audio Processor Block STV82x6 Figure 8: Audio Processor Block Diagram HPD LS IN (From Digital Audio Matrix) LS_SRD_CTRL (5Bh) LS_STS_GAIN (5Ch) LS_STS_FREQ (5Dh) LS_SRS_SPACE (5Eh) LS_SRS_CENTER (5Fh) Loudspeaker Processing LS_BAL(69h) LS_VOL_CTRL(67h) LS_CVOL(68h) Volume Spatial Effects Low Noise Audio SRS CUT_ID (00h) (L+R)/2 Woofer Lowpass SW_BAND (6Bh) SW_GAIN (6Ah) ANA_LS_HP (07h) BEEPER_CTRL (79h) BEEPER_TONE (7Ah) Beeper Volume HP IN (From Digital Audio Matrix) HP_BAL (77h) Volume (L+R)/2 1 0 Low Noise Audio Mute ANA_LS_HP (07h) SVC_SEL (59h) SVC_CTRL (5Ah) SW_ON ANA_LS_HP (07h) HP_BT_CTRL (71h) HP_BASS_GAIN (72h) HP_TREB_GAIN (73h) HP_VOL_CTRL (75h) HP_CVOL (76h) Headphone Processing Note: The audio signals available on the IS and SCART outputs are not affected by any digital or analog matrix processing. 3.2 Smart Volume Control (SVC) The Smart Volume Control (SVC) feature is designed to process sound level variations caused by changes in signal sources (e.g. when switching channels) or in volume (e.g. when advertisements are broadcast). The SVC is controlled by the SVC_ON bit in the SVC_CTRL register. When the SVC_ON bit is set, the Smart Volume Control prevents annoying volume changes by automatically adjusting the selected sound source (demodulator or SCART) to a programmable reference level before audio processing. The regulation ranges from +6 dB to -30 dB with a fast attenuation and a programmable slow amplification. The fast attenuation reduces audio peak (and potential clipping) and slow amplification is a compromise between regulation recovery and limited audio amplification during audio silence. The programmable output reference level must be defined to prevent internal clipping depending on the selected audio processing boosting functions such as Surround (up to +9 dB), Equalizer or Bass/Treble (up to +12 dB) and Loudness (up to +6 dB). When the SVC is enabled, recommended reference values are -18 dB for the Loudspeaker path and -9 dB for the Headphone path. When the SVC is disabled, it acts as a wide-range prescaler (between -30 dB and +15.5 dB) before audio-processing to prevent internal clipping depending on the selected functions (see above). If 16/95 HP OUT Bass/ Treble Smart Volume Control Balance SW OUT Gain SVC_SEL (59h) SVC_CTRL (5Ah) LS_EQ_CTRL (60h) LS_EQ_BAND1 (61h) LS_EQ_BAND2 (62h) LS_EQ_BAND3 (63h) LS_EQ_BAND4 (64h) LS_EQ_BAND5 (65h) LS_LOUD(66h)_ Mute LS OUT Smart Volume Control Loudness 5-band Equalizer Balance STV82x6 Audio Processor Block required, it complements the dedicated prescaler for FM, NICAM or SCART sources. The internal level can be measured using the peak detector. The SVC can be used either in the Loudspeaker or Headphone path (but not both simultaneously). When used in the Headphone path, the SVC prevents the sound level from becoming suddenly too strong, causing ear damage. The SVC is configured in registers SVC_SEL and SVC_CTRL. 3.3 ST WideSurround STV82x6 offers three preset ST WideSurround effects on the Loudspeaker path: Music, a concert hall effect Movie, for films on TV Simulated Stereo, which generates a pseudo-stereo effect from mono source "ST WideSurround" is an extension of the conventional stereo concept which improves the spatial characteristics of the sound. This could be done simply by adding more speakers and coding more channels into the source signal as is done in the cinema, but this approach is too costly for normal home use. The ST WideSurround system exploits a method of phase shifting to achieve a similar result using only two speakers. It restores spatiality by adding artificial phase differences. The Surround/Pseudo-stereo mode is automatically selected by the Automatic Standard Recognition System (AUTOSTD) depending on the detected stereo or mono source. By default, "Movie" is selected for Surround mode. This value may be changed to "Music" by the STS_MODE bit in the LS_SRD_CTRL register. Additional user controls are provided to better adapt the spatial effect to the source. The ST WideSurround Gain (LS_STS_GAIN) and ST WideSurround Frequency (LS_STS_FREQ) registers can be used to enhance music predominance in Music mode and theater effect + voice predominancy in Movie mode. 3.4 5-Band Audio Equalizer The Loudspeaker audio spectrum is split into 5 frequency bands and the gain of each of them can be adjusted within a range from -12 dB to +12 dB in steps of 1 dB. The Audio Equalizer may be used to pre-define frequency band enhancement features dedicated to various kinds of music or to attenuate frequency resonances of loudspeakers or the listening environment. The Equalizer is enabled by the EQ_ON bit in the LS_EQ_CTRL register. The Bass, Medium and Treble values are programmed in registers LS_EQ_BAND[1:5]. Figure 9: Equalizer f1=100Hz f2=330Hz f3=1KHz f4=3.3KHz f5=6.6KHz 3.5 Bass/Treble Control The gain of bass and treble frequency bands for the headphone can be also tuned within a range from -12 dB to +12 dB in steps of 1 dB. It may be used to pre-define frequency band enhancement 17/95 Audio Processor Block STV82x6 features dedicated to various kinds of music, to implement programmable Loudness or Super-bass functions. The Headphone Bass/Treble feature is enabled by setting the BT_ON bit in the HP_BT_CTRL register. The Bass and Treble gain values are adjusted in registers HP_BASS_GAIN and HP_TREBLE_GAIN, respectively. 3.6 Volume/Balance Control The STV82x6 provides a Volume/Balance Control for each of the Loudspeaker, Subwoofer and Headphone audio outputs. Its wide range (from 0 to -96 dB in a linear scale) largely covers typical home applications (approx. 60 dB) while maintaining a good S/N ratio. Its fine resolution (0.375 dB) provides simple volume programming and a relative OSD scale representation. The Loudspeaker, Subwoofer and Headphone volume values should be programmed progressively in steps of less than 1 dB in order to prevent audible envelope variations and a minimum duration of 16 ms is required between two successive programming commands to guarantee that there are no audible plops during volume changes. In this case, a full 8-bit volume scan with minimum steps of 0.375 dB will last approximately 4 s (minimum). Figure 10: Volume Control Output Gain 0 dB -96 dB Mute 00h IC Control FFh The Volume/Balance Control can operate in one of two different modes: In Differential mode (default value), the volume control is a common volume value for both the Left and Right Loudspeaker and Headphone channels. In Independent mode, the volume for the Left and Right channels for Loudspeakers or Headphone is controlled independently. As the Loudspeaker bass frequencies are output by the Subwoofer, its reference volume is controlled by default with the value of the LS_CVOL common volume register. The SW_GAIN register value is used to adjust the level of the Subwoofer output in regards to this reference. In Independent mode, the SW_GAIN register is used as a separated volume control and does not take into account the Loudspeaker audio level. 3.6.1 Differential Mode The common value for the Right/Left volume controls for the Loudspeaker, Subwoofer and Headphone outputs are programmed in registers LS_CVOL, SW_GAIN and HP_CVOL, respectively. A differential balance can be applied using registers LS_BAL and HP_BAL to adjust the Left/Right level ratio as shown in Figure 11. 18/95 STV82x6 Audio Processor Block Figure 11: Differential Balance Output Gain 100% nn el Le ha C ft tC ha ig h nn R el Mute 80h 00h IC Control 7Fh 3.6.2 Independent Mode This is enabled by setting the BAL_MODE bits in both the LS_VOL_CTRL and HP_VOL_CTRL registers to Independent mode. In this case, the register values are used to control the volume/ balance functions as described in Table 6. Table 6: Volume/Balance Control Registers LS_CVOL/LS_VOL_L HP_CVOL/HP_VOL_L Register 68h/76h LS_VOL_CTRL (Loudspeaker Volume Control) BAL_MODE = 0 (Independent Mode) BAL_MODE = 1 (Differential Mode) LS_VOL_L Left Volume value LS_CVOL Common Right/Left Volume value LS_VOL_R Right Volume value LS_BAL Differential Balance value Mode LS_BAL/LS_VOL_R HP_BAL/HP_VOL_R Register 69h/77h HP_VOL_CTRL (Headphone Volume Control) BAL_MODE = 0 (Independent Mode) BAL_MODE = 1 (Differential Mode) HP_VOL_L Left Volume value HP_CVOL Common Right/Left Volume value HP_VOL_R Right Volume value HP_BAL Differential Balance value 3.6.3 Mute Control An Independent Mute Control can be used to smooth audio envelope variations in order to prevent any audible plops can be applied to all audio outputs. This feature is controlled by register ANA_LS_HP. A Headphone Detection Mode that will automatically mute the Loudspeaker and Subwoofer outputs when a headphone is detected can be enabled by the HDP_ON bit in the ANA_LS_HP register. In this case, only the Headphone output will remain active. See also Section 3.8: Subwoofer Control and Section 5.4: Headphone Detection. When a demodulated source is selected on the audio output, the mute is also controlled by Automatic Standard Recognition system (AUTOSTD). In case of no mono detected or bad detection of language without backup, the corresponding audio output is automatically muted. In case of multi-language, the output will be de-muted by selecting an other language with backup. 19/95 Audio Processor Block STV82x6 Table 7: Headphone/Mute Register Configuration ANA_LS_HP Register HPD_IN X X X X 0 1 Output Status MUTE_SW X 0 1 0 0 0 HPD_ON 0 X X 0 1 1 SW_ON 0 1 X 1 0 0 MUTE_LS 0 0 1 0 0 0 MUTE_HP 0 1 1 0 0 0 Muted SW HP Active LS, HP Stereo LS & SW LS, SW & HP (Channel Change: Mute All) LS, SW & HP Mono SW & HP SW & LS LS (Default) HP Stereo 3.7 Automatic Loudness Control As the human ear does not hear the audio frequency range the same way depending on the power of the audio source, the Loudness Control corrects this effect by sensing the volume level and then boosting bass and treble frequencies proportionally to middle frequencies at lower volume. While maintaining the amplitude of the 1 kHz components at an approximately constant value, the gain values of lower and higher frequencies are automatically progressively amplified up to +18 dB when the audio volume level decreases.The maximum treble amplification can be adjusted from 0 dB (first order loudness) to +18 dB (second order loudness). As the volume is proportional to the external audio amplification power, the loudness amplification threshold is programmable in order to tune the absolute level. The Loudspeaker Loudness function is enabled by setting the LOUD_ON bit in register LS_LOUD. The Loudness Threshold and Maximum Treble Gain values are also programmed in this register. Two bass cut-off frequencies are available: 40 Hz for Normal mode 120 Hz for Bass Amplified mode The mode is selected by the LOUD_FREQ bit in register LS_LOUD (66h). 3.8 Subwoofer Control The subwoofer signal is created by adding the bass frequency of the Left/Right Loudspeaker channels. The Subwoofer output is enabled by setting the SW_ON bit in register ANA_LS_HP. This will also force the Headphone output into Mono mode. The Subwoofer Gain and Frequency Bandwidth values are programmed in registers SW_GAIN and SW_BAND, respectively. The cut-off frequency can be adjusted from between 50 and 400 Hz in steps of 50 Hz. 3.9 Beeper The beeper is used to replace the audio signal with a tone on the Loudspeaker or Headphone outputs. It can be used for various applications such as beep sounds for remote control, alarm clock or other features. 20/95 STV82x6 The Beeper operates in one of two modes: Audio Processor Block Pulse mode (beep applications) A tone with a programmable short duration (between 128 ms and 1 s) is generated. Afterwards, the beeper is automatically disabled and the output is switched back to the audio signal. Continuous mode (alarm application) A tone with a programmable long duration is generated. Its start and stop controls must be programmed by IC. In both modes, it is recommended to use the mute function to smooth the audio-to-beeper and beeper-to-audio (Continuous mode only) transitions. The second transition is automatically muted in Pulse mode. Beeper parameters are controlled in register BEEPER_CTRL. The beeper tone level and frequency are programmed in register BEEPER_TONE. The level (or volume) ranges between 0 dB and -93 dB in steps of 3 dB and the tone frequency ranges between 62.2 Hz and 8 kHz in steps of 1 octave. A beep generator is shared only by the Loudspeaker or Headphone outputs. Therefore, in the event of simultaneous beeps when in Pulse mode, only the first beep will define the effective duration that will be the same for both outputs. Note: The audio output is not affected by the Automatic Mute Control of Automatic Standard Recognition function when the beeper is activated. Figure 12: Pulse Mode BEEP_ON = 1 BEEP_ON = 0 0.125s < T < 1s T predefined 62.5 Hz < F < 8 kHz Figure 13: Continuous Mode BEEP_ON = 1 T defined by IC write BEEP_ON = 0 62.5 Hz < F < 8 kHz 3.10 SRSTM 3D Surround (STV8226/36 only) In addition to ST WideSurround, the STV8226/36 provides SRSTM 3D Stereo and Mono outputs which are spatial effects patented by SRS Labs. The SRSTM system is available on the IC when the SRS_ON bit of register CUT_ID is set (STV8226/36 identification). ST and SRSTM Surround systems cannot be used simultaneously. These signals are output only on the Loudspeaker path. 21/95 Audio Processor Block STV82x6 SRSTM creates a fully immersed three-dimensional soundfield through the use of a standard 2-speaker stereo configuration. For monaural audio, the source is first converted into a synthetic stereo signal before creating the 3D effect. The virtual gain for the Surround and Center components can be adjusted by registers LS_SRS_SPACE and LS_SRS_CENTER (respectively) in Stereo mode only. These values are used to adapt spatial effects to the source. For ST WideSurround Sound, Stereo or Mono output mode is automatically selected by the Automatic Standard Recognition System (AUTOSTD) according to the detected audio source. By default, ST WideSurround Sound is selected. SRSTM Surround is selected in register LS_SRD_CTRL. 22/95 STV82x6 Audio Matrices 4 Audio Matrices In addition to the sound carrier source (SIF), the STV82x6 accepts up to three analog stereo audio inputs (2 VRMS SCART compatible) and one analog mono audio input (0.5 VRMS). These different sources can go back out through four analog stereo audio outputs which are Loudspeaker + Subwoofer and Headphone (1 VRMS) and two compatible SCART audio outputs (2 VRMS). An extra digital stereo output (IS compatible) is available for interfacing with a Dolby Pro Logic Decoder or an external Digital-to-Analog Converter (DAC). Figure 14: Audio Matrix Block Diagram CH_SEL (49h) Lang. Select SIF Demodulator Demod. Matrix CH_MX (48h) SW1 CH_LANG (4Ah) CH_SEL (49h) Lang. Select SW2 CH_LANG (4Ah) SDI IS IS Matrix CH_MX (48h) Audio DSP Low Noise Mute D/A D/A LS SW (LSL, LSR) SW IS SDO Low Noise Mute CH_SEL (49h) Lang. Select Audio DSP D/A HP (HPL, HPR) ANA_SCART (06h) MONOIN Mono In A/D SW3 CH_LANG (4Ah) CH_SEL (49h) Low Noise Mute SCART Matrix SW5 CH_MX (48h) (AI1L, AI1R) SCART1 In SW4 Low Noise Switch Level Prescaling Lang. Select CH_LANG (4Ah) D/A ANA_SCART (06h) (AI2L, AI2R) SCART2 In SCART1 Out (AO1L, AO1R) SW6 Low Noise Mute Low Noise Switch (AI3L, AI3R) SCART3 In ANA_SCART (06h) SCART2 Out (AO2L, AO2R) SW7 Low Noise Mute Low Noise Switch 23/95 Audio Matrices STV82x6 4.1 Input Audio Matrix The mono input (MONOIN) and three stereo SCART inputs (AI1L, AIR1), (AI2L, AI2R) and (AI3L, AI3R) can be switched to any audio output and the same source can be connected to different outputs. The inputs can totally bypass the STV82x6 functions (Thru mode) via the full analog SCART path or use the audio processing corresponding to the different audio outputs. The input matrix is programmed in bits DSP_ISCART_SEL[1:0] of register ANA_SCART. In Thru mode, the STV82x6 is switched into Low Power mode (Standby) and the audio matrix configuration (ANA_SCART register) is memorized and is not reset when switched back to Full Power mode. See Section 7.2: Standby Mode. Before processing the audio signal, the selected analog input is converted into a digital 16-bit signal and pre-processed. Its sound level can be prescaled within a range between -6 dB and +6 dB in steps of 1 dB (register PRE_AUX) and for Left/Right channels (register CH_MX). The internal level can be measured with the Peak Level Detector. 4.2 Output Audio Matrix The Loudspeaker+Subwoofer (LSL, LSR, SW), Headphone (HPL, HPR) and IS (SDO) outputs can directly select two possible sources which are either the demodulated signal or the converted audio input (from the SCART or mono input) in register CH_SEL. In the event of a dual mono source, the language is selected in register CH_LANG. The two analog SCART outputs (AO1L, AO1R) and (AO2L, AO2R) can be used to bypass the STV82x6 functions by directly selecting the analog input SCARTs or the output digital source from the demodulator or the converted audio input (with prescaling and Left/Right re-matrixing). The SCART output is selected in register ANA_SCART and the digital source in register CH_SEL. In the event of a dual mono source, the language is selected in register CH_LANG as other audio outputs. In the event of a demodulator source selection, the mute is automatically controlled for all audio outputs. 24/95 STV82x6 Additional Controls and Flags 5 5.1 Additional Controls and Flags Interrupt Request The identified TV sound standard is displayed in register AUTO_STAT. Each change in the detected standard is flagged to the host system via hardware pin IRQ. The flag must be reset by reprogramming the IRQ bit in register AUTO_CTRL and then checking the detected standard status by reading registers AUTO_STAT, NICAM_STAT, ZWT_STAT and CH_MX. 5.2 IC Bus Expander Pins BUS0 and BUS1 can be used to control external switchable IF SAW filters or audio switches. These pins can be directly programmed by register CTRL. 5.3 Stereo Flag For Loudspeakers only, a Stereo Mode Detection flag (the ST_ID bit in register AUTO_STAT) is set when a demodulated source is selected and a stereo standard is detected. The stereo flag is also output on pin ST in order to control an external indicator (e.g. LED). The stereo mode is also displayed by status register AUTO_STAT. CAUTION: When the IS input is selected, the stereo flag is no longer available on pin ST. 5.4 Headphone Detection For the headphone, the HPD input can be used to automatically mute the Loudspeaker and Subwoofer outputs when the HPD_ON bit is set in register ANA_LS_HP (active low). The HPD pin must be set for the mute function to be active. Figure 15: Headphone Detection STV82x6 Loudspeaker Audio Processing Audio Matrix Mute Control Subwoofer Audio Processing Right Left Subwoofer Headphone Detection Headphone Audio Processing IC Control 25/95 IS Interface STV82x6 6 IS Interface A digital stereo input is available for a virtual Dolby source from an external decoder. A digital stereo output (IS compatible) is available for routing the demodulated signal or a converted input audio signal into a Dolby Pro Logic Decoder or an external DAC. The STV82x6 IS interface drives the serial bus (SCK, WS, SDO) in Master mode in format 32.fs with a sampling frequency (fS) of 32 kHz. An additional master clock (MCK) in format 256.fs (fS = 8.192 MHz) is provided if required for the slave interface. Both Philips and Sony modes are supported with programmable Word Selection (WS) polarity (register I2S). By default, all IS digital outputs are set in high impedance and must be switched to low impedance via register CTRL before use. A clock system output (SYSCK) is also available for clock peripherals using the same quartz frequency as the STV82x6. By default, this clock output (identical to the crystal oscillator) is set to high impedance and must be switched to low impedance via register CTRL before use. 26/95 STV82x6 Power Supplies 7 7.1 Power Supplies Supply Voltages The STV82x6 supports different power configurations due to its integrated voltage regulators. Typically, two power supplies, which are grouped into two sets of IC pins, are required. 1. Digital Power Supply (DPS) This supply may be either 3.3 V or 5 V if an external power transistor is used. The DPS supplies pins VDD1, VDD2 and VDDP. -- In 3.3 V mode, the power is directly supplied to the digital power pins. In this case, the REG pin is not used and must be connected to the ground. -- 5 V mode requires the use of an external transistor coupled to the integrated voltage regulator via the REG pin in order to generate a stable 3.3 V supply to the digital power pins. 2. Analog Power Supply (APS) This supply may be either 8 V or 5 V. In both cases, external resistors are required, except for pin VDDH. The APS supplies pins VDDIF, VDDC, VDDA and VDDH. -- The 8 V power supply is directly connected to pin VDDH and offers a 2 VRMS dynamic voltage on SCART outputs. The other analog power pins can be supplied with an 8 V or 5 V supply through external resistors. -- If only a 5 V power supply is available for pin VDDH, the SCART outputs will be reduced to 1 VRMS. In this case, the SEL5V bit must be set in register ANA_CTRL. Figure 16: 3.3 V / 8 V or 3.3 V / 5 V Application Standby 3.3 V DPS VDDIF VDDC VDDA 8 or 5 V APS REG Digital 3.3 V Regulator Analog 3.3 V Regulator Audio Buffer VDD1 VDD2 Digital Core Analog Core VDDH VDDP Clock Generator STV82x6 27/95 Power Supplies Figure 17: 5 V / 8 V or 5 V / 5 V Application Standby 5V DPS VDDIF VDDC VDDA 8 or 5 V APS STV82x6 REG Digital 3.3 V Regulator Analog 3.3 V Regulator Analog Core Audio Buffer VDD1 VDD2 Digital Core VDDH VDDP Clock Generator STV82x6 7.2 Standby Mode The STV82x6 provides a Thru mode configuration that bypasses IC functions via a SCART I/O pin (Full Analog Path only). In this case, only minimum power is required (Standby mode). In Standby mode, the digital and analog power supplies are switched off, except for pins VDDA and VDDH which are used to maintain the SCART path, the last configuration programmed for analog matrixing (register ANA_SCART) and the power configuration (register ANA_CTRL). When switching back to normal Full Power mode, all IC registers are reset except for those used in Standby mode to maintain the original configuration. In Standby mode, the IC bus does not operate. However, the bus can still be used by other ICs since the IC I/O pins (SDA and SCL) of the STV82x6 are forced into a high-impedance configuration. 28/95 STV82x6 IC Bus 8 8.1 IC Bus IC Address and Protocol The STV82x6 IC interface works in Slave mode and is fully compliant with IC standards in Fast mode (maximum frequency of 400 kHz). Two pairs of IC chip addresses are used to connect two STV82x6 chips to the same IC serial bus. The device address pairs are defined by the polarity of the ADR pin and are listed in the following table: Table 8: IC Read/Write Addresses ADR LOW (connected to GND1) HIGH (connected to VDD1) Write address (hex) (W) 80h A0h Read address (hex) (R) 81h A1h Protocol Description Write Protocol Start W A Sub-address A Data A .... A Data A Stop Read Protocol Start W A Sub-address A Stop Start R A Data A .... A Data N W = Write address, R = Read address, A = Acknowledge, N = No acknowledge. Sub-address is the register address pointer; this value auto-increments for both write and read. The STV82x6 cannot immediately reply to an IC read request when addressing DSP registers (addresses 40h and greater).The IC interface holds the IC Serial Clock (SCL) line low before each data byte is read to compensate for the latency of the DSP response (64 s in worst case). The implemented IC Pulling Down mode is compatible with a Continuous or Stopped SCL when held low (restart at high level, if stopped) and operates between 24 kHz and 400 kHz. If SCL Pulling Down mode is not supported by the Master IC interface, the Pulling Down system can be deactivated by setting the SCLPD_OFF bit in register RESET. In this case, two successive reads of the same DSP register are required and only the second one is valid (first read is `don't care'). This special protocol is no longer compatible with the IC sub-address auto-incrementation function in Read mode. 8.2 STV82x6 Reset All STV82x6 features are controlled via the IC bus. However, the device is designed to power up into a fully working default mode without having to be sent IC bus data to set it up. The STV82x6 can be "reset" in 2 ways: 1. By Software via the IC bus: This clears all synchronous logic, except for the IC bus registers. 2. By Hardware via the RESET pin: In addition to clearing all synchronous logic, the RESET input (active low) resets all the IC bus registers to the default values listed below. 29/95 IC Bus STV82x6 Table 9: RESET Default Values Function Demodulation Auto-standard Scanned Standards FM Deviation Audio Outputs Automatic Mute Mode Loudspeaker Source Loudspeaker Volume Loudspeaker L/R Balance Subwoofer Headphone Source Headphone Automatic Detection Headphone Volume Headphone L/R Balance SCART-1 out SCART-2 out IS out Audio Processing Loudspeaker/Headphone SVC Loudspeaker Surround Loudspeaker 5-Band Equalizer Loudspeaker Loudness Headphone Bass/Treble Loudspeaker/Headphone Beeper OFF, 0 dB Reference Value OFF OFF, 0 dB (Flat Band) OFF OFF, 0 dB (Flat Band) -48 dB / OFF ON Demodulated Sound -48 dB / muted L/R = 100% -48 dB / OFF Demodulated Sound ON -48 dB / Muted L/R = 100% Demodulated Sound SCART1 Source OFF ON M/N, B/G, I, L/L' 125 kHz (Max.) Default mode 30/95 STV82x6 Register List 9 Note: Register List The unused bits (defined as reserved) in IC registers must be kept to zero. The system clock registers (from address 08h to 0Bh) do not need to be modified if a standard 27 MHz quartz crystal is used The demodulator registers (from address 0Ch to 54h) default values are optimum and any change is not recommended, except for: AGCS (0Fh) to adjust AGC gain for AM carrier in L/L' standard (AGC used in open loop) CAROFFSET1(22h) and CAROFFSET2(3Ah) to compensate IF carrier frequency with an outof-standard offset Soundlevel Prescaling PRE_FM(44h), PRE_NICAM(45h) and PRE_AUX(46h) to equalize demodulated or external audio signal before audio processing. Peak detector registers PEAK_DET_CTRL(4Bh) and PEAK_DET_STAT(4Ch) can be used to measure internal sound level. Sound source selection for each audio output channel Loudspeaker+Subwoofer, Headphone, SCART and IS to be done using CH_SEL(49h) In Multi-lingual mode, CH_LANG(4Ah) selects separately the language for each audio output channel. AUTO_CTRL(50h) to select between L/L' or D/K/K1/K2/K3 standard which can be discriminated automatically. To be used also to change maximum FM deviation (125 kHz, by default) in case of wide overmodulation. AUTO_SCKM(51h) and AUTO_SCKST(52h) to define the list of mono and stereo standards to be recognized automatically. Note: () used in reset value column means that the bit or the byte is read-only. (S) symbol indicates that the field value is represented in signed binary format. (*) The field AGC_ERR[4:0] (AGCS) can be written by user if the bit AGC_CMD (AGCC) is set to one (by default controlled by AUTOSTD). To be used to adjust manually the input gain of analog AGC amplifier for AM carrier (L/L'). 9.1 IC Register Map By default, all IC registers controlled by Automatic Standard Recognition System (AUTOSTD) are forced to Read-only mode for the user. These registers and bits are shaded in Table 10. Table 10: List of IC Registers (Sheet 1 of 5) Addr. Reset (Hex) Value (Bin) Register Function and Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name IC General Control CUT_ID RESET CTRL I2S 00h 02h 03h 04h (0001 0001) 0000 0000 0000 0000 0000 0000 SRS_ON 0 0 0 0 SCLPD_OF AUTO_OFF F BUS_EXPAND[1:0] 0 0 0 IS_EN 0 CUT_NUMBER[5:0] 0 SDI_EN I2S_STD SOFT_LRS T1 0 I2S_WSPO L SOFT_LRS T2 MCK_EN 0 SOFT_RST SYSCK_EN 0 31/95 Register List Table 10: List of IC Registers (Sheet 2 of 5) Addr. Reset (Hex) Value (Bin) Register Function and Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x6 Name Bit 0 Audio Mute & Switch ANA_CTRL ANA_SCART ANA_LS_HP 05h 06h 07h 0000 0000 0010 1100 (0)100 0111 SEL5V 0 0 MUTE_OSC ART2 SW_ON 0 0 0 MUTE_OSC ART1 MUTE_LS 0 0 DSP_ISCART_SEL[1:0] HPD_IN HPD_ON OSCART2_SEL[1:0] 0 0 OSCART1_SEL[1:0] MUTE_SW MUTE_HP Clocking PLL_DIV PLL_MD PLL_PEH PLL_PEL 08h 09h 0Ah 0Bh 0000 0101 0001 1110 0000 0001 1110 1000 0 0 0 0 0 0 0 0 0 PE1[7:0] SDIV[2:0] MD2[4:0] PE1[11:8] FDIV[2:0] Demodulator DEMOD_CTRL DEMOD_STAT AGCC AGCS DCS 0Ch 0Dh 0Eh 0Fh 10h 0000 0110 (0000 0000) 0001 0001 (0000 0000) (0000 0000) 0 0 AGC_ CMD 0 0 0 0 0 0 0 0 QPSK_LK AM_SEL FM2_CAR AGC_REF[2:0] AGC_ERR[4:0] (*) DC_ERR[7:0] DEMOD_MODE[2:0] FM2_SQ FM1_CAR FM1_SQ AGC_CST[1:0] SIG_OVER SIG_UNDE R Demodulator Channel 1 CARFQ1H CARFQ1M CARFQ1L FIR1C0 FIR1C1 FIR1C2 FIR1C3 FIR1C4 FIR1C5 FIR1C6 FIR1C7 ACOEFF1 BCOEFF1 CRF1 CETH1 SQTH1 CAROFFSET1 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 0011 1110 1000 0000 0000 0000 0000 0000 1111 1110 1111 1100 1111 1101 0000 0010 0000 1101 0001 1000 0001 1111 0010 0011 0001 0010 (0000 0000) 0010 0000 0011 1100 0000 0000 CARFQ1[23:16] CARFQ1[15:8] CARFQ1[7:0] FIR1C0[7:0] (S) FIR1C1[7:0] (S) FIR1C2[7:0] (S) FIR1C3[7:0] (S) FIR1C4[7:0] (S) FIR1C5[7:0] (S) FIR1C6[7:0]6 (S) FIR1C7[7:0] (S) ACOEFF1[7:0] BCOEFF1[7:0] CRF[7:0] (S) CETH1[7:0] SQTH1[7:0] CAROFFSET1[7:0] (S) Demodulator Channel 2 IAGCR IAGCC 25h 26h 1000 1000 0000 0011 IAGC_ OFF 0 0 IAGC_REF[7:0] 0 0 IAGC_CST[2:0] 32/95 STV82x6 Table 10: List of IC Registers (Sheet 3 of 5) Addr. Reset (Hex) Value (Bin) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah (0000 0000) 0100 0100 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0100 0001 0100 0010 0101 1001 0000 1010 1100 0001 1100 (0000 0000) (0000 0000) 0010 0000 0011 1100 0000 0000 Register List Register Function and Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name IAGCS CARFQ2H CARFQ2M CARFQ2L FIR2C0 FIR2C1 FIR2C2 FIR2C3 FIR2C4 FIR2C5 FIR2C6 FIR2C7 ACOEFF2 BCOEFF2 SCOEFF SRF CRF2 CETH2 SQTH2 CAROFFSET2 IAGC_CTRL[7:0] CARFQ2[23:16] CARFQ2[15.8] CARFQ2[7:0] FIR2C0[7:0] (S) FIR2C1[7:0] (S) FIR2C2[7:0] (S) FIR2C3[7:0] (S) FIR2C4[7:0] (S) FIR2C5[7:0] (S) FIR2C6[7:0] (S) FIR2C7[7:0] (S) ACOEFF2[7:0] BCOEFF2[7:0] SCOEFF[7:0] SRF[7:0] (S) CRF2[7:0] (S) CETH2[7:0] SQTH2[7:0] CAROFFSET2[7:0] (S) NICAM NICAM_CTRL NICAM_BER NICAM_STAT 3Dh 3Eh 3Fh 0000 0000 (0000 0000) (0000 0000) NIC_DET F_MUTE LOA 0 0 0 0 ERROR[7:0] CBI[4:1] NIC_MUTE 0 DIF_POL ECT MAE Stereo FM ZWT_CTRL ZWT_STAT 40h 41h 0011 0001 (0000 0000) 0 0 STD_MODE 0 0 THRESH[3:0] 0 0 ZW_DET TSCTRL[1:0] ZW_ST ZW_DM Sound Preprocessing & Selection FM_DCL FM_DCR PRE_FM PRE_NICAM PRE_AUX CH_CTRL CH_MX CH_SEL CH_LANG 42h 43h 44h 45h 46h 47h 48h 49h 4Ah (0000 0000) (0000 0000) 0000 0110 0000 1101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 MUTE_D01 2 0 0 0 0 I2S_PRESCALE[3:0] (S) MUTE_D12 NIC_DMX NICDPH_O FF FM_DCL[7:0] (S) FM_DCR[7:0] (S) FM_PRESCALE[5:0] (S) NICAM_PRESCALE[5:0] (S) SCART_PRESCALE[3:0] (S) FM_DMX[1:0] FMDPH_OF F FMDPH_S W I2S_MX[1:0] I2S_SEL[1:0] I2S_LANG[1:0] SC_MX[1:0] SC_SEL[1:0] SC_LANG[1:0] DEMOD_MX[3:0] HP_SEL[1:0] HP_LANG[1:0] LS_SEL[1:0] LS_LANG[1:0] 33/95 Register List Table 10: List of IC Registers (Sheet 4 of 5) Addr. Reset (Hex) Value (Bin) 4Bh 4Ch 4Dh 0000 0000 (0000 0000) (0000 0000) STV82x6 Register Function and Description Bit 7 0 Name Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 PEAK_DET_CTRL PEAK_DET_STATL PEAK_DET_STATR PD_SEL[1:0] PEAK_LEVEL_LEFT[7:0] PEAK_LEVEL_RIGHT[7:0] Automatic Standard Recognition System AUTO_CTRL AUTO_SCKM AUTO_SCKST AUTO_TIMER AUTO_STAT 50h 51h 52h 53h 54h 0000 0001 0000 1111 0001 1111 1010 0100 0(000 0000) 0 0 LDK_ZWT3 0 0 0 0 IRQ 0 LDK_NIC SINGLE_SH OT LDK_SCK I_NIC DK_DEV[1:0] I_SCK BG_ZWT BG_SCK BG_NIC LDK_SW MN_SCK MN_ZWT LDK_ZWT2 LDK_SWT1 FM_TIME[1:0] ST_ID NICAM_TIME[2:0] AUTO_ON STEREO_SID[1:0] ZWEITON_TIME[2:0] MONO_SID[1:0] STEREO_S MONO_STA TATE TE Audio Processing SVC_SEL SVC_CTRL LS_SRD_CTRL LS_STS_GAIN LS_STS_FREQ LS_SRS_SPACE LS_SRS_CENTER LS_EQ_CTRL LS_EQ_BAND1 LS_EQ_BAND2 LS_EQ_BAND3 LS_EQ_BAND4 LS_EQ_BAND5 LS_LOUD LS_VOL_CTRL LS_CVOL/ LS_VOL_L LS_BAL/ LS_VOL_R SW_GAIN SW_BAND 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 0000 0000 0000 0000 0000 0000 1000 0000 00010101 1000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 0001 1000 0000 EQ_ON 0 0 0 0 0 LOUD_TH_ ON 0 0 0 0 0 0 0 0 0 0 0 SVC_ON SRD_ON 0 0 0 0 0 SVC_REF[4:0] (S) 0 0 SRD_SEL SRD_STER STS_MODE EO 0 SVC_SW SVC_TIME[1:0] 0 0 ST_GAIN[7:0] BASS_FREQ[1:0] MEDIUM_FREQ[1:0] TREBLE_FREQ[1:0] SRS_SPACE[7:0] (for Stereo mode only) SRS_CENTER[7:0] (for Stereo mode only) 0 0 0 0 0 0 LOUD_TH[2:0] 0 0 CVOL[7:0] 0 0 0 0 R EQ_BAND1_GAIN[4:0] (S) EQ_BAND2_GAIN[4:0] (S) EQ_BAND3_GAIN[4:0] (S) EQ_BAND4_GAIN[4:0] (S) EQ_BAND5_GAIN[4:0] (S) LOUD_ FREQ 0 0 LOUD_TH_GHR[2:0] 0 BAL_MODE 69h 6Ah 6Bh 0000 0000 1000 0000 0000 0011 0 0 0 BAL[7:0] (S) SW_GAIN[5:0] 0 0 SW_FREQ[2:0] Headphone Channel HP_BT_CTRL HP_BASS_GAIN HP_TREBLE_GAIN HP_VOL_CTRL 71h 72h 73h 75h 0000 0000 0000 0000 0000 0000 0000 0001 BT__ON 0 0 0 0 0 0 0 0 0 0 0 BASS_GAIN[4:0] (S) TREBLE_GAIN[4:0] (S) BAL_MODE 0 0 34/95 STV82x6 Table 10: List of IC Registers (Sheet 5 of 5) Addr. Reset (Hex) Value (Bin) 76h 1000 0000 Register List Register Function and Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name HP_CVOL/ HP_VOL_L HP_BAL/ HP_VOL_R CVOL[7:0] 77h 0000 0000 BAL[7:0] (S) Beeper BEEPER_CTRL BEEPER_TONE 79h 7Ah 0000 0000 0111 0000 LS_BEEP_ ON HP_BEEP_ BEEP_MOD ON E 0 0 0 BEEP_VOL[4:0] BEEP_DURATION[1:0] BEEP_FREQ[2:0] 9.2 STV82x6 General Control Registers CUT_ID Version Identification Address (hex): 00h Type: R Bit 7 SRS_ON Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CUT_NUMBER[5:0] Bit Name SRS_ON Reset 0 Identifies the STV82x6 version Function 0: version without SRSTM (STV82x6) - Only ST WideSurround can be used 1: version with SRSTM (STV8226/36) - Both SRSTM and ST WideSurround are available Bit 6 CUT_NUMBER[5:0] 0 Reserved. 010001 Dice Version Identification RESET Address (hex): 02h Type: R/W Bit 7 0 Bit 6 SCLPD_OFF Software Reset Register Bit 5 AUTO_OFF Bit 4 0 Bit 3 0 Bit 2 Bit 1 Bit 0 SOFT_RST SOFT_LRST1 SOFT_LRST2 Description The built-in Automatic Standard Recognition System (AUTOSTD) can be disabled by bit AUTO_OFF (when high). In this case, the Software Reset function (bits SOFT_LRESTART1 and SOFT_LRESTART2) can be used to implement the Automatic Standard Recognition by IC Software. This is not required if the built-in Automatic Standard Recognition System function is used (default). 35/95 Register List STV82x6 Bit Name Bit7 SCLPD_OFF Reset 0 Reserved. SCL Pulling-down System Disable 0: System is enabled 1: System is disabled Function AUTO_OFF 0 Automatic Standard Recognition System Disable 0: System is enabled 1: System is disabled Bits[4:3] SOFT_LRESTART1 SOFT_LRESTART2 SOFTRST 00 0 0 0 Reserved. Softreset (active high) of Channel 1 detectors only. Softreset (active high) of Channel 2 detectors only. General softreset (active high) to reset all hardware registers except for IC data. CTRL Address (hex): 03h Type: R/W Bit 7 0 Bit 6 Hardware Interface Control Register Bit 5 Bit 4 I2S_EN Bit 3 SDI_EN Bit 2 0 Bit 1 MCK_EN Bit 0 SYSCK_EN BUS_EXPAND[1:0] Description Provides all hardware controls to drive external components (SAW Filter, Audio Switches) and additional Audio Decoder (Dolby Pro Logic) via register I2S including the Master and Quartz Clocks. Bit Name Bit 7 BUS_EXPAND[1:0] I2S_EN SDI_EN Bit 2 MCK_EN Reset 0 00 0 0 0 0 Reserved. Function Static control by IC of hardware pins BUS1 and BUS0. When 1, the IS hardware pin is enabled (SCK, WS, SDO) When 1, the SDI input pin is enabled (switch with ST output). Must be used when IS mode is selected. Reserved. Master Clock Enable Enables the master clock output (256.fs) to interface by IS with the Dolby Pro Logic Decoder. 0: Disabled. 1: Enabled SYSCK-EN 0 System Clock Enable Enables the system clock output to provide the quartz clock required to interface with the Dolby Pro Logic Decoder. 0: Disabled. 1: Enabled 36/95 STV82x6 I2S Address (hex): 04h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 I2S_STD Bit 2 I2S_WSPOL Bit 1 0 Register List IS Interface Control Register Bit 0 0 Description Proposes most used IS standard (Philips and Sony) with Word Select (WS) polarity programming. Only Master mode is supported. All interfaced chip must be set in slave mode. Bit Name Bits[7:4] I2S_STD Reset 0000 0 Reserved. IS Standard Select 0: Philips Standard (Default) 1: Sony Standard Function I2S_WSPOL 0 IS Word Select Polarity Select 0: No WS inversion (Default) 1: WS with polarity inversion Bits[1:0] 00 Reserved. 9.3 Analog Block ANA_CTRL Power Supply Configuration Control Register Address (hex): 05h Type: R/W Bit 7 SEL5V Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit Name SEL5V Reset 0 5 V Analog Power Supply Select Function The audio power amplifiers should be muted before changing this bit. 0: 8 V Analog Power Supply (Default). 1: 5 V Analog Power Supply Bit[6:0] 0000000 Reserved 37/95 Register List ANA_SCART Address (hex): 06h Type: R/W Bit 7 Bit 6 Bit 5 MUTE_OSCA RT2 Bit 4 Bit 3 Bit 2 MUTE_OSCA RT1 Bit 1 STV82x6 SCART Control Register Bit 0 DSP_ISCART_SEL[1:0] OSCART2_SEL[1:0] OSCART1_SEL[1:0] Bit Name DSP_ISCART _SEL[1:0] Reset 00 Function Analog Audio Matrixing for Mono and SCART Inputs (with Low Noise Audio Switching) 00: ISCART1 (Default) 01: ISCART2 10: ISCART3 11: Mono input MUTE_OSCART2 OSCART2_SEL [1:0] 1 01 0: No Mute 1: x Output muted Analog Audio Matrixing for SCART outputs (with Low Noise Audio Switching) 00: DSP_OSCART 01: ISCART1 (Default) 10: ISCART2 11: ISCART3 MUTE_OSCART1 OSCART1_SEL [1:0] 1 00 0: No Mute 1: x Output muted 00: DSP_OSCART (Default) 01: ISCART1 10: ISCART2 11: ISCART3 Note: SCART IC programming (matrixing and mute control) is maintained during Standby mode Before switching to Standby mode, the output SCART mute is recommended if the demodulated sound source (DSP_OSCART) is selected by this output. This source might cause an audible plop during the digital power down. ANA_LS_HP ANA_LS/HP Address (hex): 07h Type: R/W Bit 7 HPD_IN Bit 6 HPD_ON Loudspeaker/Subwoofer/Headphone Mute Control Bit 5 SW_ON Bit 4 0 Bit 3 0 Bit 2 MUTE_LS Bit 1 MUTE_SW Bit 0 MUTE_HP 38/95 STV82x6 Register List Bit Name HPD_IN Reset 0 Headphone Input Pin Status Function Read only IC bit that displays the HPD pin Status 0: Headphone is detected 1: Headphone is not detected HPD_ON 0 Headphone Detection Enable 0: Headphone Detection is disabled 1: Headphone Detection is enabled. If the HPD_IN bit is set, the Loudspeaker and Subwoofer mute is activated SW_ON 0 Subwoofer Enable Before switching on/off the subwoofer, a mute is recommended to prevent an audible plop. 0: Subwoofer is disabled. Headphone output is selected. 1: Subwoofer is enabled. Subwoofer output is selected and Headphone output is in Mono mode Bits[4:3] MUTE_LS MUTE_SW MUTE_HP 00 000 Reserved. 000: LS + SW + HP mono 001: LS + SW 010: LS + HP stereo 011: LS only 100: Not used. 101: Not used. 110: HP stereo only. 111: All muted (Default) 9.4 Clocking A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described below. By default, the programming is defined for a 27-MHz quartz crystal frequency, which is the frequency recommended for reducing potential RF interference in the application. (See Section 2.2: System Clock.) However, if necessary, the PLL Clock can be re-programmed for other quartz crystal frequencies within a range from 23 to 30 MHz. Other quartz crystal frequencies can be programmed on your demand. Note: A Crystal Frequency change is compatible with other default IC programming including the built-in Automatic Standard Recognition System. PLL_DIV Address (hex): 08h Type: R/W Bit 7 0 Bit 6 0 PLL Frequency Divider Register Bit 5 Bit 4 SDIV[2:0] Bit 3 Bit 2 Bit 1 FDIV[2:0] Bit 0 Bit Name Bits[7:6] SDIV[2:0] FDIV[2:0 Reset 00 000 101 Reserved. PLL Frequency S-Divider PLL Frequency F-Divider Function 39/95 Register List PLL_MD Address (hex): 09h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 MD2[4:0] Bit 1 STV82x6 PLL Coarse Frequency Control Register Bit 0 Bit Name Bits[7:5] MD2[4:0] Reset 000 11110 Reserved. PLL Coarse Frequency Control Function PLL_PEH Address (hex): 0Ah Type: R/W Bit 7 0 Bit 6 0 PLL Fine Frequency Control Register (MSBs) Bit 5 0 Bit 4 0 Bit 3 Bit 2 PE1[11:8] Bit 1 Bit 0 Bit Name Bits[7:4] PE1[11:8] Reset 000 0001 Reserved. PLL Fine Frequency Control (4 MSBs) Function PLL_PEL Address (hex): 0Bh Type: R/W Bit 7 Bit 6 PLL Fine Frequency Control Register (LSBs) Bit 5 Bit 4 PE1[7:0] Bit 3 Bit 2 Bit 1 Bit 0 Bit Name PE1[7:0] Reset 11101000 PLL Fine Frequency Control (8 LSBs) Function 40/95 STV82x6 Register List 9.5 Demodulator DEMOD_CTRL Demodulator Control Register Address (hex): 0Ch Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 AM_SEL Bit 2 Bit 1 DEMOD_MODE[2:0] Bit 0 Bit Name Bits[7:4] AM_SEL Reset 0000 0 Reserved. Demodulator Configuration Select Function 0: FM configuration of demodulator (Default) 1: AM configuration of demodulator DEMOD_MODE[ 2:0] 110 Demodulator Mode Select CH1 FM X00: X01: 010: 011: 110: 111: Normal Wide Normal Wide Normal Wide CH2 FM/QPSK FM Normal FM Wide QPSK System B/G/L/D/K QPSK System B/G/L/D/K QPSK System I QPSK System I DEMOD_STAT Address (hex): 0Dh Type: R Bit 7 0 Bit 6 0 Demodulator Detection Status Register Bit 5 0 Bit 4 QPSK_LK Bit 3 FM2_CAR Bit 2 FM2_SQ Bit 1 FM1_CAR Bit 0 FM1_SQ Bit Name Bit [7:5] QPSK_LK Reset 000 0 Reserved. QPSK Lock detection flag 0: Not detected 1: Detected Function FM2_CAR 0 Channel 2 FM/AM Carrier detector flag 0: Not detected 1: Detected FM2_SQ 0 Channel 2 FM Squelch detector flag 0: Not detected 1: Detected 41/95 Register List STV82x6 Bit Name FM1_CAR Reset 0 Channel 1 FM/AM Carrier detector flag 0: Not detected 1: Detected Function FM1_SQ 0 Channel 1 FM Squelch detector flag 0: Not detected 1: Detected Note: These registers allow direct access to the demodulator signal detectors. AGCC Address (hex): 0Eh Type: R/W Bit 7 AGC_CMD Bit 6 0 AGC Control for IF ADC Bit 5 0 Bit 4 Bit 3 AGC_REF[2:0] Bit 2 Bit 1 Bit 0 AGC_CST[1:0] Bit Name AGC_CMD Reset 0 Automatic Gain Control Command Mode Function Normally set to 0 enabling automatic mode. For L/L' standards, the AGC should be switched off due to the presence of the AM sound carrier. In this case, a fixed gain value should be set using the AGCS register. 0: Automatic mode. AGC controlled by the AUTOSTD function. (Default) 1: Manual/Forced mode Bits[6:5] AGC_REF[2:0] 00 100 Reserved. This bitfield is used to defines the clipping level which adjusts the allowable proportion of samples at the input of the ADC which will be clipped. The AGC tries to maximize the use of the full scale range of the ADC. The default setting gives a ratio of 1/256. Clipping Ratio 000: 001: 010: 011: AGC_CST[1:0] 01 1/16 (Single carrier) 1/32 1/64 1/128 100: 101: 110: 111: Clipping Ratio 1/256 (Default 1/512 1/1024 1/2048 (Multiple carriers) AGC Time Constant This is the time constant between each step of 1.25 dB by the ADC. Step Duration (ms) 00 01 10 11 1.33 2.66 5.33 10.66 42/95 STV82x6 AGCS Address (hex): 0Fh Type: R Bit 7 0 Bit 6 Bit 5 Bit 4 AGC_ERR[4:0] Bit 3 Bit 2 Bit 1 SIG_OVER Register List AGC Control and Status for IF ADC Bit 0 SIG_UNDER Bit Name Bit 7 AGC_ERR[4:0] Reset 0 00000 Reserved. Amplifier Gain Control Function This is the Gain Control value of ADC. There are 31 steps of +1.25 dB (see Note below). 00000: 0 dB Gain 11110: +37.5 dB Gain SIG_OVER 0 AGC Input SIgnal Upper Threshold 0: Normal signal 1: Signal too large and AGC is overloaded SIG_UNDER 0 AGC Input SIgnal Lower Threshold 0: Normal signal 1: Signal too small and AGC is underloaded When the AGC is in Automatic mode (AGC_CMD = 0), bits SIG_OVER and SIG_UNDER indicate if the input signal is too small/large and the AGC is under/overloaded. This is useful when setting the STV82x6 SIF input level. Note: When AGC_CMD = 0, AGC_ERR[4:0] can be read -- indicating the input level. It can also be written to -- presetting the AGC level which will then adjust itself to the final value. When AGC_CMD = 1, the AGC is off and writing to AGC_ERR[4:0] directly controls the AGC amplifier gain. Reading AGC_ERR just confirms the fixed value. DCS Address (hex): 10h Type: R Bit 7 Bit 6 DC Offset Status for IF ADC Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DC_ERR[7:0] Bit Name DC_ERR[7:0] Reset 00000000 DC offset error of IF ADC output Function 43/95 Register List STV82x6 9.6 Demodulator Channel 1 CARFQ1H, CARFQ1M, CARFQ1LChannel 1 Carrier DCO Frequency Address (hex): 13h to 15h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CARFQ1[23:16], CARFQ1[15:8], CARFQ1[7:0] Bit Name CARFQ1[13:8] ]CARFQ1[13:8] CARFQ1[7:0] Reset 00111110 10000000 00000000 Function Channel 1 DCO Carrier Frequency (8 MSBs) Channel 1 DCO Carrier Frequency Channel 1 DCO Carrier Frequency (8LSBs) Table 11: Mono Carrier Frequencies by System System M/N B/G I L D/K/K1/K2 Mono Carrier Freq. (MHz) 4.5 5.5 6.0 6.5 6.5 CARFQ1[23:0] (dec) 3072000 3754667 4096000 4453717 4437333 CARFQ1[23:0] (hex) 2EE000h 394AABh 3E8000h 43F555h 43B555h Note: Carrier Freq: CARFQ1(dec).Fs/224 with Fs = 24.576 MHz (crystal oscillator frequency independent) FIR1C[0:7] Address (hex): 15h to 1Ch Type: R/W Bit 7 Bit 6 Channel 1 FIR Coefficients Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIR1C0[7:0] to FIR1C7[7:0] Bitfield FM 27 kHz FIR1C0[7:0] FIR1C1[7:0] FIR1C2[7:0] FIR1C3[7:0] FIR1C4[7:0] FFh FEh FEh 00h 06h FM 50 kHz 00h FEh FCh FDh 02h Description FM 200 kHz 00h 01h 01h FCh 08h FM 350 kHz 02h 01h FCh 03h 04h FM 500 kHz 01h 00h 04h FAh 05h AM 00h FEh FDh FEh 04h 44/95 STV82x6 Register List Bitfield FIR1C5[7:0] FIR1C6[7:0] FIR1C7[7:0] 0Eh 16h 1Bh 0Dh 18h 1Fh Description F6h F8h 4Ah F2h 06h 43h 00h F2h 4Dh 0Dh 16h 1Dh ACOEFF1 Address (hex): 1Dh Type: R/W Bit 7 Bit 6 Channel 1 Baseband PLL Loop Filter Proportional Coefficient Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACOEFF1[7:0] Bit Name ACOEFF1[7:0] Reset 00100011 Function Used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 1) Defines the damping factor of the loop. For values, refer to Table 12. BCOEFF1 Channel 1 Baseband PLL Loop Filter Integral Coefficient & DCO Gain Address (hex): 1Eh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BCOEFF1[7:0] Bit Name BCOEFF1[7:0] Reset 00010010 Function Used to program the Integral Coefficient of the baseband PLL loop filter and DCO gain Defines the bandwidth of the loop. For values, refer to Table 12. Table 12: Baseband PLL Loop Filter Adjustment (FM Mode) FM Mode ACOEFF (hex) BCOEFF (hex) FM_DEV max (kHz) DCO Range (kHz) Small 10h 1Ah 62.5 96 Standard 22h 12h 125 192 Medium 2Ch 0Ah 250 384 Large 2Ch 0Ah 500 768 A2 Standard 10h 11h 125 192 45/95 Register List CRF1 Address (hex): 1Fh Type: R Bit 7 Bit 6 Bit 5 Bit 4 CRF1[7:0] Bit 3 Bit 2 Bit 1 STV82x6 Channel 1 Baseband PLL Demodulator Offset Bit 0 Bit Name CRF1[7:0] Reset 00000000 Channel 1 Carrier Recovery Frequency Function Displays the instantaneous frequency offset of the Channel 1 Baseband PLL Demodulator. CETH1 Address (hex): 20h Type: R/W Bit 7 Bit 6 Channel 1 FM/AM Carrier Level Threshold Bit 5 Bit 4 CETH1[7:0] Bit 3 Bit 2 Bit 1 Bit 0 Bit Name CETH1[7:0] Reset 00100000 Function This register is used to compare the carrier level in the channel and the threshold value. This level is measured after the channel filter and is relative to the full scale reference level (0 dB). This is used as part of the validation of an FM signal, if the carrier level is below the threshold, the signal is considered to be non-valid. CETH FFh 80h 40h 20h Threshold (dB) -6 -12 -18 -24 (Default CETH 10h 08h 00h Threshold (dB) -32 -38 OFF (all carrier levels are accepted) SQTH1 Address (hex): 21h Type: R/W Bit 7 Bit 6 Channel 1 FM Squelch Threshold Register Bit 5 Bit 4 Bit 3 SQTH1[7:0] Bit 2 Bit 1 Bit 0 46/95 STV82x6 Register List Bit Name SQTH1[7:0] Reset 00111100 Function The squelch detector measures the level of high frequency noise (> 40 kHz) and compares it to the threshold level (SQTH). If the level is below this value, the S/N of the FM signal is considered to be acceptable. Values are given for FM with standard deviation. SQTH FAh 77h 3Ch 23h 19h S/N (dB) 0 10 15 (Default) 20 25 CAROFFSET1 Address (hex): 22h Type: R/W Bit 7 Bit 6 Channel 1 DCO Carrier Offset Compensation Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CAROFFSET1[7:0] (S) Bit Name CAROFFSET1[7:0] Reset 00000000 Function This value is used correct the carrier frequency offset of the incoming IF signal. Automatic frequency control in FM mode can be implemented by registers FM_DCR and FM_DCL. A DCO frequency offset (in two's complement format) is added to the pre-programming value by AUTOTSD in the CARFQ1 registers (corresponding to the standard IF carrier frequency). The programmable carrier offset ranges from -192 kHz to +190.5 kHz with a resolution of 1.5 kHz. For standard FM deviation, the value displays by FM_DCL can be directly loaded in CAROFFSET1 to exactly compensate the carrier offset on Channel 1 9.7 Demodulator Channel 2 IAGCR Channel 2 Internal AGC Reference for QPSK Address (hex): 25h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IAGC_REF[7:0] Bit Name IAGC_REF[7:0] Reset 10001000 Function Sets the mean value of the internal AGC, used for QPSK demodulation. The default setting corresponds to half full scale amplitude at the baseband PLL input. 47/95 Register List IAGCC Address (hex): 26h Type: R/W Bit 7 IAGC_OFF Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 IAGC_CST[2:0] STV82x6 Channel 2 Internal AGC Time Constant for QPSK Bit 0 Bit Name IAGC_OFF Reset 0 AGC Disable 0: Internal AGC is active 1: Internal AGC is disabled Reserved. Function Bits[6:3] IAGC_CST[2:0] 0000 011 Internal AGC Programmable Step Constant. These bits control the time per step (values given for QPSK mode). The default value defines the optimum trade-off between fast settling time (for the fastest NICAM identification) and the noise immunity (minimum BER degradation) Step time (us) Time Response (ms) 000 001 010 011 100 101 110 111 703 352 176 88 44 22 11 5.5 128 64 32 16 8 4 2 0.82 IAGCS Address (hex): 27h Type: R Bit 7 Bit 6 Channel 2 Internal AGC Status for QPSK Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IAGC_CTRL[7:0] Bit Name IAGC_CTRL[7:0] Reset 00000000 Function Indicates the value of the internal AGC gain control CARFQ2H, CARFQ2M, CARFQ2LChannel 2 Carrier DCO Frequency Address (hex): 28H to 2Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CARFQ2[23:16], CARFQ2[15.8], CARFQ2[7:0] 48/95 STV82x6 Register List Bit Name CARFQ2[23:16] CARFQ2[15.8] CARFQ2[7:0] Reset 01000100 01000000 00000000 Function Channel 2 DCO Carrier Frequency (8 MSBs) Channel 2 DCO Carrier Frequency Channel 2 DCO Carrier Frequency (8 LSBs) See Table 13. Table 13: Stereo Carrier Frequencies by System System M/N A2+ B/G NICAM BG A2 I NICAM L NICAM DK NICAM DK1 A2* DK2 A2* DK3 A2* Stereo Carrier Freq. (MHz) 4.724212 5.85 5.7421875 6.552 5.85 5.85 6.258125 6.7421875 5.7421875 CARFQ2[23:0] (Dec) 3225062 3993600 3920000 4472832 3993600 3993600 4272000 4602667 3920000 CARFQ2[23:0] (Hex) 3135E6h 3CF000h 3BD080h 444000h 3CF000h 3CF000h 412F80h 463B2Bh 3BD080h FIR2C[0:7] Address (hex): 2Bh to 32h Type: R/W Bit 7 Bit 6 Channel 2 FIR Coefficients Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIR2C0[7:0] to FIR2C7[7:0] Table 14: Channel 2 FIR Coefficients Description Bitfield FM 27 kHz FIR2C0[7:0] FIR2C1[7:0] FIR2C2[7:0] FIR2C3[7:0] FIR2C4[7:0] FIR2C5[7:0] FIR2C6[7:0] FIR2C7[7:0] FFh FEh FEh 00h 06h 0Eh 16h 1Bh FM 50 kHz 00h FEh FCh FDh 02h 0Dh 18h 1Fh QPSK 40% 00h 00h FFh 03h 00h F4h 0Ah 3Dh QPSK100% 00h 00h 00h 00h FFh 04h 14h 25h 49/95 Register List ACOEFF2 Address (hex): 33h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x6 Channel 2 Baseband PLL Loop Filter Proportional Coefficient Bit 0 ACOEFF2[7:0] Bit Name ACOEFF2[7:0] Reset 10010000 Function This value defines the loop clamping factor used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 2). See Table 15 and Table 16. BCOEFF2 Channel 2 Baseband PLL Loop Filter Integral Coefficient & DCO Gain Address (hex): 34h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BCOEFF2[7:0] Bit Name BCOEFF2[7:0] Reset 10101100 Function This value defines the loop bandwidth used to program the Integral Coefficient of the Baseband PLL loop filter and DCO gain. See Table 15 and Table 16. Table 15: Baseband PLL Loop Filter Adjustments (FM Mode) FM mode ACOEFF (hex) BCOEFF (hex) FM_DEV max (kHz) DCO Range (kHz) Small 10h 1Ah 62.5 96 Standard 22h 12h 125 192 Mid 2Ch 0Ah 250 384 Wide 2Ch 0Ah 500 768 A2 standard 10h 11h 125 192 Table 16: Baseband PLL Loop Filter Adjustments (QPSK Mode) QPSK mode ACOEFF (hex) BCOEFF (hex) DCO_DEV max (kHz) Small 90h ACh 2.84375 Medium 90h A3h 5.6875 Large 90h 9Ah 11.375 Extra-large 90h 91h 22.75 50/95 STV82x6 SCOEFF Address (hex): 35h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List Channel 2 Symbol Tracking Loop Coefficients Bit 0 SCOEFF[7:0] Bit Name SCOEFF[7:0] Reset 00011100 Function This value is used to program the proportional and integral coefficients of the QPSK Symbol tracking loop. See Table 17 and Table 18. Table 17: QPSK System - BG/L/DK Standards (40% Roll-off) Extra-Small SCOEFF (hex) 1Eh Small 25h Medium 24h Large 26h Extra-Large 2Ah Open Loop 80h Table 18: QPSK System - I Standard (100% Roll-off) Extra-Small SCOEFF (hex) 16h Small 1Dh Medium 1Ch Large 23h Extra-Large 22h SRF Address (hex): 36h Type: R/W Bit 7 Bit 6 Channel 2 Symbol Tracking Loop Frequency Bit 5 Bit 4 SRF[7:0] Bit 3 Bit 2 Bit 1 Bit 0 Bit Name SRF[7:0] Reset 00000000 Function Displays in two's complement format the frequency deviation between the incoming NICAM bitstream and the quartz clocks. The maximum error is 250 ppm. CRF2 Address (hex): 37h Type: R Bit 7 Bit 6 Channel 2 Baseband PLL Demodulator Offset Bit 5 Bit 4 CRF2[7:0] Bit 3 Bit 2 Bit 1 Bit 0 51/95 Register List STV82x6 Bit Name CRF2[7:0] Reset 00000000 Function Channel 2 Carrier Recovery Frequency. Displays the instantaneous frequency offset of the Channel 2 Baseband PLL CETH2 Address (hex): 38h Type: R/W Bit 7 Bit 6 Channel 2 FM Carrier Level Threshold Bit 5 Bit 4 CETH2[7:0] Bit 3 Bit 2 Bit 1 Bit 0 Bit Name CETH2[7:0] Reset 00100000 Function This register is used to compare the carrier level in the channel and the threshold value. This level is measured after the channel filter and is relative to the full scale reference level (0 dB). This is used as part of the validation of an FM signal, if the carrier level is below the threshold, the signal is considered to be non-valid. CETH FFh 80h 40h 20h Threshold (dB) -6 -12 -18 -24 (Default CETH 10h 08h 00h Threshold (dB) -32 -38 OFF (All carrier levels are accepted) SQTH2 Address (hex): 39h Type: R/W Bit 7 Bit 6 Channel 2 FM Squelch Threshold Bit 5 Bit 4 Bit 3 SQTH2[7:0] Bit 2 Bit 1 Bit 0 Bit Name SQTH2[7:0] Reset 00111100 Function The squelch detector measures the level of high frequency noise (> 40 kHz) and compares it to the threshold level (SQTH). If the level is below this value, the S/N of the FM signal is considered to be acceptable. Values are given for FM with standard deviation. SQTH FAh 77h 3Ch 23h 19h S/N (dB) 0 10 15 (Default) 20 25 52/95 STV82x6 CAROFFSET2 Address (hex): 3Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List Channel 2 DCO Carrier Offset Compensation Bit 0 CAROFFSET2[7:0] (S) Bit Name CAROFFSET2 [7:0] Reset 00000000 Function This value is used to correct the carrier frequency offset of the incoming IF signal. Automatic frequency control in FM mode can be implemented by registers FM_DCR and FM_DCL. A DCO frequency offset (in two's complement format) is added to the pre-programming value by AUTOTSD in the CARFQ2 registers (corresponding to the standard IF carrier frequency). The programmable carrier offset ranges from -192 kHz to +190.5 kHz with a resolution of 1.5 kHz. For standard FM deviation, the value displayed by register FM_DCR can be directly loaded in in register CAROFFSET2 to exactly compensate the carrier offset on Channel 2. 9.8 NICAM Registers NICAM_CTRL NICAM Decoder Control Register Address (hex): 3Dh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 DIF_POL Bit 1 ECT Bit 0 MAE Bit Name Bits[7:3] DIF_POL ECT Reset 00000 0 0 Reserved. Function 0: No polarity inversion (Default) 1: Polarity inversion of the differential decoding Error Counter Timer: Defines the NICAM error measurement period 0: 128 ms (Default) 1: 64 ms MAE 0 Max. Allowed Errors. Defines the NICAM error decoding for mute function. 0: 511 Max (Default) 1: 255 Max 53/95 Register List NICAM_BER Address (hex): 3Eh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x6 NICAM Bit Error Rate Register Bit 0 ERROR[7:0] Bit Name ERROR[7:0] Reset 00000000 NICAM Error Counter Value Function NICAM_STAT Address (hex): 3Fh Type: R Bit 7 NIC_DET Bit 6 F_MUTE NICAM Detection Status Register Bit 5 LOA Bit 4 Bit 3 CBI[3:0] Bit 2 Bit 1 Bit 0 NIC_MUTE Bit Name NIC_DET Reset 0 NICAM Signal Detect 0: NICAM signal no detected 1: NICAM signal detected Function F_MUTE 0 Frame Mute 0: No mute 1: Mute due to Superframe Alignment Loss LOA 0 Loss of Frame Alignment Word (FAW) 0: No Alignment Lost 1: Frame Alignment Word Lost CBI[3:0] NIC_MUTE 0000 0 Indicates the received NICAM control bits Indicates the NICAM decoder mute 9.9 Zweiton ZWT_CTRL Zweiton Detector Control Register Address (hex): 40h Type: R/W Bit 7 0 Bit 6 STD_MODE Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 THRESH[3:0] TSCTRL[1:0] 54/95 STV82x6 Register List Bit Name Bit 7 STD_MODE THRESH[3:0] Reset 0 0 1100 Reserved. 0: German standard (Default) 1: Korean standard Function Defines the threshold of the detector for pilot and tone frequencies. Level (% of the mid scale) 0000 0001 0010 0011 0100 0101 0110 0111 0 6.25 12.5 18.75 25 31.25 37.5 43.75 Level (% of the mid scale) 1000 1001 1010 1011 1100 (Default) 1101 1110 1111 50 56.25 62.5 68.75 75 81.25 87.5 93.75 TSCTRL[1:0] 00 Defines both the detection time and the error probability (reliability of the detection). Sample Accumulation 00 01 (Default) 10 11 1024 1024 2048 2048 Decision Count 2 3 2 3 Time (ms) 256 384 512 768 Error Probability 10-4 10-6 10-7 10-9 ZWT_STAT Address (hex): 41h Type: R Bit 7 0 Bit 6 0 Zweiton Status Register Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 ZW_DET Bit 1 ZW_ST Bit 0 ZW_DM Bit Name Bits[7:3] ZW_DET ZW_ST ZW_DM Reset 00000 0 0 0 Reserved. Pilot Detection Flag Stereo Tone Detection Flag Dual Mono Tone Detection Flag Function 9.10 Sound Preprocessing and Selection Registers FM_DCL FM DC Offset Left Register Address (hex): 42h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FM_DCL[7:0] 55/95 Register List STV82x6 Bit Name FM_DCL[7:0] Reset 00000000 Function Displays (in two's complement format) the FM (or AM) DC offset level after demodulation on channel 1 (and removed automatically). In FM mode, the DC offset value gives a direct value of the carrier frequency offset which is used to compensate the DCO with the CAROFFSET1 value in the event of an out-of-standard offset. The range and the resolution depend upon the FM bandwidth programmed defined in register BCOEFF1. See Table 19. FM_DCR Address (hex): 43h Type: R Bit 7 Bit 6 FM DC Offset Right Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FM_DCR[7:0] Bit Name FM_DCR[7:0] Reset 00000000 Function Displays (in two's complement format) the FM (or AM) DC offset level after demodulation on channel 2 (and removed automatically). In FM mode, the DC offset value gives a direct value of the carrier frequency offset which is used to compensate the DCO with the CAROFFSET2 value in the event of an out-of-standard offset. The range and the resolution depend upon the FM bandwidth programmed defined in register BCOEFF2. See Table 19. Table 19: FM_DCL/R Range and Resolution FM mode Small Standard & A2 Standard Medium Large Range (kHz) 96 192 384 768 Resolution (kHz) 0.750 1.5 3 6 PRE_FM Address (hex): 44h Type: R/W Bit 7 0 Bit 6 0 FM Prescaling Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FM_PRESCALE[5:0] Bit Name Bits[7:6] Reset 0 Reserved. Function 56/95 STV82x6 Register List Bit Name FM_PRESCALE [5:0] Reset Function 000110 -6 to + 24 dB FM (or AM) prescaling to normalize the FM (or AM) demodulated signal level before audio processing. Auto level control can be implemented by IC software using the Peak Level Detector. (Default value = +6 dB) 011000 010111 010110 010101 010100 G (dB) +24 +23 +22 +21 +20 etc. 111110 111101 111100 111011 111010 G (dB) -2 -3 -4 -5 -6 PRE_NICAM Address (hex): 45h Type: R/W Bit 7 0 Bit 6 0 NICAM Prescaling Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NICAM_PRESCALE[5:0] Bit Name Bits[7:6] NICAM_ PRESCALE[5:0] Reset 00 Reserved. Function 001101 -6 to + 24 dB NICAM prescaling to normalize the NICAM demodulated signal level before audio processing. Auto level control can be implemented by IC software using the Peak Level Detector. (Default value = +13 dB) 011000 010111 010110 010101 010100 G (dB) +24 +23 +22 +21 +20 etc. 111110 111101 111100 111011 111010 G (dB) -2 -3 -4 -5 -6 PRE_AUX Address (hex): 46h Type: R/W Bit 7 Bit 6 SCART Prescaling Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2S_PRESCALE[3:0] SCART_PRESCALE[3:0] 57/95 Register List STV82x6 Bit Name I2S_PRESCALE [3:0] Reset 0000 Function -6 to + 6dB IS Input prescaling to normalize the incoming audio signal before audio processing. Auto level control can be implemented by IC software using the Peak Level Detector. These bits are used to adjust the corresponding incoming signal level before audio processing. 0110 0101 0100 0011 0010 0001 0000 (Default) G (dB) +6 +5 +4 +3 +2 +1 0 1111 1110 1101 1100 1011 1010 G (dB) -1 -2 -3 -4 -5 -6 SCART_PRESCAL E[3:0] 0000 -6 to + 6dB SCART Input prescaling to normalize the incoming audio signal before audio processing. Auto level control can be implemented by IC software using the Peak Level Detector. These bits are used to adjust the corresponding incoming signal level before audio processing. 0110 0101 0100 0011 0010 0001 0000 (Default) G (dB) +6 +5 +4 +3 +2 +1 0 1111 1110 1101 1100 1011 1010 G (dB) -1 -2 -3 -4 -5 -6 CH_CTRL Address (hex): 47h Type: R/W Bit 7 MUTE_D012 Bit 6 MUTE_D12 Channel Control Register Bit 5 NIC_DMX Bit 4 NICDPH_OFF Bit 3 Bit 2 Bit 1 FMDPH_OFF Bit 0 FMDPH_SW FM_DMX[1:0] Bit Name MUTE_D012 Reset 0 Function 0: LS/HP/SC/IS channel unmuted 1: If DEMOD source is selected as OUTPUT channel by CH_SEL and CH_LANG, then MUTE_LS/MUTE_HP/MUTE_SC signal are set (LS/HP/SC/IS channel mute) 0: LS/HP/SC/IS channel unmuted 1: If DEMOD_1 or DEMOD_2 source is selected as OUTPUT channel by CH_SEL and CH_LANG, then MUTE_LS/MUTE_HP/MUTE_SC signal are set (LS/HP/SC/IS channel mute) When 1, Reverse Left/Right Channel to take into account the case where the mono signal would be carried on the Right Channel. 0: NICAM De-emphasis (Default) 1: Bypass NICAM De-emphasis FM Stereo Dematrix 00 (Default) 01 10 11 DeMatrix L=CH1, R=CH2 L=CH1+CH2, R=CH1-CH2 L=2CH1-CH2, R=CH2 L=(CH1+CH2)/2, R=(CH1+CH2)/2 Standard No matrixing Kor. Zweiton (A2+) & Radio German Zweiton (A2, A2*) Stereo to Mono MUTE_D12 0 NIC_DMX NICDPH_OFF FM_DMX[1:0] 0 0 00 58/95 STV82x6 Register List Bit Name FMDPH_OFF FMDPH_SW Reset 0 0 0: FM De-emphasis (Default) 1: Bypass FM De-emphasis 0: 50 s FM De-emphasis (Default) 1: 75 s FM De-emphasis Function CH_MX Address (hex): 48h Type: R/W Bit 7 Bit 6 Channel Matrix Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2S_MX[1:0] SC_MX[1:0] DEMOD_MX[3:0] Bit Name I2S_MX[1:0] SC_MX[1:0] DEMOD_MX[3:0] Reset 00 00 0000 Function IS Matrixing. Programmable values are listed in Table 20. SCART Matrixing. Programmable values are listed in Table 20. Demodulator Matrixing. Programmable values are listed in Table 21. Table 20: SCART and IS Matrixing SC_0/I2S_0 Left 00 01 10 11 CH_L CH_R CH_L CH_R SC_1/I2S_1 Left 0 0 CH_R CH_L Right CH_R CH_L Right Table 21: Demodulator Matrixing DEMOD_0 Left 0X00 0X01 0X10 0X11 1000 1001 1010 FM_L NIC_L NIC_L FM_L NIC_L FM_L NIC_L FM_L FM_R NIC_R DEMOD_1 Left 0 0 0 0 FM_R NIC_R NIC_R DEMOD_2 Left 0 0 0 0 0 0 0 Right Right 59/95 Register List Table 21: Demodulator Matrixing (Continued) DEMOD_0 Left 1011 11XX FM_L FM_L STV82x6 DEMOD_1 Left NIC_L NIC_L DEMOD_2 Left NIC_R 0 Right Right CH_SEL Address (hex): 49h Type: R/W Bit 7 Bit 6 Channel Source Selection Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2S_SEL[1:0] SC_SEL[1:0] HP_SEL[1:0] LS_SEL[1:0] Bit Name I2S_SEL[1:0] SC_SEL[1:0] HP_SEL[1:0] LS_SEL[1:0] Reset 00 00 00 00 Source Channel Selection. 0X: Demodulated sound (Default) 10: SCART 11: IS Function Note: A mute of the corresponding audio output is recommended before switching between Demodulated sound and SCART source. Any audio discontinuity might create annoying audible plops. CH_LANG Address (hex): 4Ah Type: R/W Bit 7 Bit 6 Channel Language Selection Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2S_LANG[1:0] SC_LANG[1:0] HP_LANG[1:0] LS_LANG[1:0] Bit Name I2S_LANG[1:0] SC_LANG[1:0] HP_LANG[1:0] LS_LANG[1:0] Reset 00 00 00 00 Function Channel Language Selection. See Table 4 and Table 5. 00: Not to be used. 01: Mono A 10: Mono B 11: Mono C Note: 1 Refer to Table 4 and Table 5 for selecting Channel Language, Sound and System values. 60/95 STV82x6 Register List 2 A mute of the corresponding audio output is recommended before changing the language. Any audio discontinuity might create annoying audible plop. PEAK_DET_CTRL Address (hex): 4Bh Type: R Bit 7 0 Bit 6 0 Peak Level Detector Control Register Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 PD_SEL[1:0] Bit Name Bits[7:2] PD_SEL[1:0] Reset 000000 Reserved. 00 Peak Level Detector Source Selection 00: FM 01: NICAM 10: SCART 11: IS Function PEAK_DET_STATL Address (hex): 4Ch Type: R Bit 7 Bit 6 Peak Level Detector Status Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEAK_LEVEL_LEFT[7:0] Bit Name PEAK_LEVEL_ LEFT[7:0] Reset 00000000 Function Displays the Absolute Peak Level of the audio source selected. The measured value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB) down to 1/ 256 of the full scale (-48 dB). In AM/FM Mono mode, only the PEAK_LEVEL_LEFT[7:0] value must be taken into account. In FM Mono mode, the audio peak level range depends upon the programmed FM bandwidth. The unique difference is that the measurement is done after Sound pre-processing (DC offset removal, Prescaling, De-emphasis and Dematrixing). In FM Stereo mode, the maximum value may be used to check if the incoming signal level is correctly adjusted by the prescaling factor or if there are no FM overmodulation problems (clipping). Programmable values are listed in Table 19. The difference between the PEAK_LEVEL_LEFT[7:0] and PEAK_LEVEL_RIGHT[7:0] values may be calculated by the microcontroller to identify Mono or Stereo mode from an unknown source (SCART or IS). 61/95 Register List PEAK_DET_STATR Address (hex): 4Dh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x6 Peak Level Detector Status Register Bit 0 PEAK_LEVEL_RIGHT[7:0] Bit Name PEAK_LEVEL_ RIGHT[7:0] Reset 00000000 Function Displays the Absolute Peak Level of the audio source selected. The measured value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB) down to 1/256 of the full scale (-48 dB). For more information, refer to register PEAK_DET_STATL. 9.11 Automatic Standard Recognition AUTO_CTRL Automatic Standard Recognition Control Register Address (hex): 50h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 IRQ Bit 3 SINGLE_SHOT Bit 2 Bit 1 Bit 0 LDK_SW DK_DEV[1:0] Bit Name Bits[7:5] IRQ Reset 000 0 Reserved. Function This flag (output on IRQ pin) is set to ON by the AUTOSTD when the standard recognition status has changed. The external microprocessor will detect this signal and will run the OSD procedure. This procedure must first reset via IC the IRQ flag and then read the detection status in the registers (NICAM_STAT, ZWT_STAT, AUTO_STAT and CH_MX) SINGLE_SHOT 0 Single Shot Mode Selection 0: Single Shot mode is not selected 1: Single Shot mode is selected1 DK_DEV[1:0] 00 Selects FM deviation configuration to take into account of overmodulation in DK_NICAM standard. 00: FM 50 kHz (Default) 01: FM 200 kHz 10: FM 350 kHz 11: FM 500 kHz LDK_SW 1 Makes exclusive the auto search of DK/K1/K2/K3 and L/L' standard 0: DK/K1/K2/K3 standard auto-search / L/L' disabled 1: L/L' standard auto-search / DK/K1/K2/K3 disabled 1. Single_Shot mode can be used before disabling the Automatic Standard Recognition (AUTOSTD) to pre-program demodulator registers in a defined standard and reduce IC programming in Manual mode 62/95 STV82x6 Note: Register List Only standard deviation FM 50K kHz is compatible with other D/K1/K2/K3 standards in Automatic Standard Recognition Search mode. It has to be deselected when programs with larger FM deviation are broadcast (reserved only for D/K-Mono or D/K NICAM standard). FM deviation superior to 350 kHz will degrade strongly NICAM reception due to overlapping of FM and QPSK IF spectrum in DK-NICAM standard. L/L' and DK/K1/K2/K3 standard can be discriminated in Automatic Standard Recognition Search mode because the same frequency is used for the mono IF carrier. AUTO_SCKM Address (hex): 51h Type: R/W Bit 7 0 Bit 6 0 Auto Standard Check Mono Register Bit 5 0 Bit 4 0 Bit 3 LDK_SCK Bit 2 I_SCK Bit 1 BG_SCK Bit 0 MN_SCK Bit Name Bits[7:4] LDK_SCK Reset 0000 1 Reserved. L/L' or D/K Mono Standard Enable 0: Disabled 1: Enabled Function I_SCK 1 I Mono Standard Enable 0: Disabled 1: Enabled BG_SCK 1 B/G Mono Standard Enable 0: Disabled 1: Enabled MN_SCK 1 M/N Mono Standard Enable 0: Disabled 1: Enabled Note: AUTOSTD is off when all mono standards are disabled. AUTO_SCKST Address (hex): 52h Type: R/W Bit 7 LDK_ZWT3 Bit 6 LDK_ZWT2 Auto Standard Check Stereo Register Bit 5 LDK_SWT1 Bit 4 LDK_NIC Bit 3 I_NIC Bit 2 BG_ZWT Bit 1 BG_NIC Bit 0 MN_ZWT 63/95 Register List STV82x6 Bit Name LDK_ZWT3 Reset 0 Function D/K3 Zweiton (A2*) Stereo Standard Enable 0: Disabled 1: Enabled LDK_ZWT2 0 D/K2 Zweiton (A2*) Stereo Standard Enable 0: Disabled 1: Enabled LDK_ZWT1 0 D/K1 Zweiton (A2*) Stereo Standard Enable 0: Disabled 1: Enabled LDK_NIC 1 D/K NICAM Stereo Standard Enable 0: Disabled 1: Enabled I_NIC 1 I NICAM Stereo Standard Enable 0: Disabled 1: Enabled BG_ZWT 1 B/G Zweiton (A2) Standard Enable 0: Disabled 1: Enabled BG_NIC 1 B/G NICAM Standard Enable 0: Disabled 1: Enabled MN_ZWT 1 M/N Zweiton (A2+) Standard Enable 0: Disabled 1: Enabled Note: Stereo standard covers all transmission modes (stereo or multi-language) of the NICAM or Zweiton (A2, A2* or A2+) system. AUTO_TIMER Address (hex): 53h Type: R/W Bit 7 Bit 6 Detection Time Out Register Bit 5 Bit 4 NICAM_TIME[2:0] Bit 3 Bit 2 Bit 1 ZWEITON_TIME[2:0] Bit 0 FM_TIME[1:0] Bit Name FM_TIME[1:0] Reset 10 FM Detection Time-out 00: 16 ms 01: 32 ms 10: 48 ms (Default) 11: 64 ms Function NICAM_TIME[2:0] 100 NICAM Detection Time-out 000: 96 ms 001: 128 ms 010: 160 ms 011: 192 ms 100: 224 ms (Default) 101: 256 ms 110: 288 ms 111: 320 ms 64/95 STV82x6 Register List Bit Name ZWEITON_TIME[ 2:0] Reset 100 Zweiton Detection Time-out 000: 256 ms 001: 512 ms 010: 768 ms 011: 1024 ms Function 100: 1280 ms (Default) 101: 1536 ms 110: 1792 ms 111: 2040 ms Note: The time-out default value is optimum and does not normally need to be changed. AUTO_STAT Address (hex): 54h Type: R Bit 7 ST_ID Bit 6 Detection Standard Status Register Bit 5 Bit 4 AUTO_ON Bit 3 Bit 2 Bit 1 Bit 0 STEREO_STA MONO_STATE TE STEREO_SID[1:0] MONO_SID[1:0] Bit Name ST_ID Reset 0 Function Stereo Mode Detection flag activated when a stereo standard coming from the demodulator selected on Loudspeaker output. Stereo transmission modes are: - Zweiton stereo (ZWT_DET&ST&DM = 110, indifferently German or Korean standard) - NICAM stereo with backup (CBI = 1000) - NICAM stereo with no backup (CBI = 0000) The stereo flag is also output on ST pin to control an external indicator (an LED, for instance) STEREO_STATE MONO_STATE 0 0 When AUTOSTD is ON and a standard has been detected, the FSM has two "stable states". These flags indicate whether the FSM is in the state "mono-det" (mono standard detected) or "stereo-det" (stereo standard detected). If at least one stereo standard is enabled, the "mono-det" state is only transitory. Automatic Standard Recognition System Status 0: Automatic Standard Recognition System is OFF 1: Automatic Standard Recognition System is ON AUTO_ON 0 STEREO_SID[1:0] MONO_SID[1:0] 00 Identification of the detected TV sound standard. See Table 22. 00 Table 22: TV Sound Standards System M/N B/G I Mono Sound (MHz) 4.5 (FM 27k) 5.5 (FM 50k) 6.0 (FM 50k) MONO_SID [1:0] 00 01 LDK_SW X X X DK_DEV [1:0] XX XX XX XX Stereo Sound (MHz) 4.724 (Zweiton A2+) 5.85 (NICAM 40%) 5.742 (Zweiton A2) 6.552 (NICAM 100%) STEREO_SID [1:0] 00 00 01 00 10 X 65/95 Register List Table 22: TV Sound Standards System L STV82x6 Mono Sound (MHz) 6.5 (AM) 6.5 (FM 50k) 6.5 (FM 200k) MONO_SID [1:0] LDK_SW 1 DK_DEV [1:0] XX 00 01 Stereo Sound (MHz) 5.85 (NICAM 40%) STEREO_SID [1:0] 00 D/K 6.5 (FM 350k) 6.5 (FM 500k) 111 0 10 11 0 XX XX XX XX 5.85 (NICAM 40%) 00 5.85 (NICAM 40%) 6.258 (Zweiton A2*) 6.742 (Zweiton A2*) 5.742 (Zweiton A2*) 00 01 10 11 D/K1/K2/ K3 0 6.5 (FM 50k) 0 0 9.12 Smart Volume Control SVC_SEL SVC Selection for Loudspeaker/Headphone Register Address (hex): 59h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 SVC_SW Bit Name Bit[7:1] SVC_SW Reset 0000000 0 Reserved Smart Volume Control Selection 0: SVC selection on Loudspeaker path 1: SVC selection on Headphone path Function SVC_CTRL Address (hex): 5Ah Type: R/W Bit 7 SVC_ON Bit 6 SVC Control Register Bit 5 Bit 4 Bit 3 Bit 2 SVC_REF[4:0] Bit 1 Bit 0 SVC_TIME[1:0] Bit Name SVC_ON Reset 0 Smart Volume Control Mode Select Function 0: Prescaling (Prevents internal clipping) 1: Automatic Level Regulation (Automatically regulates the selected sound source) 66/95 STV82x6 Register List Bit Name SVC_TIME[1:0] Reset 10 Defines the constant time of the gain loop. Function Time Constant for 6 dB Amplification 00: 01: 10: 11: SVC_REF[4:0] 00000 16 s (Default) 8s 4s 2s Smart Volume Control Reference Level Select If SVC_ON = 0, this value defines the prescaling gain ranging from -30 dB to +15.5 dB. If SVC_ON = 1, this value defines the output reference level of the regulation ranging from -2.5 dB down to -30 dB. The SVC output level must be adjusted to avoid internal clipping due to postprocessing with amplification, i.e. ST/SRSTM Surround Sound (+9 dB max), Equalizer or Bass/ Treble (+12 dB max) and Loudness (+6 dB max). Programmable values are listed in Table 23. Table 23: SVC Bit Values SVC_ON = 0 SVC_REF[4:0] > 00101 00101 00100 00011 00010 00001 00000 (Default) 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 <10110 SVC_ON = 1 SVC_REF[4:0] > 00101 00101 00100 00011 00010 00001 00000 11111 1 REF_LEVEL (dB) Reserved +15.5 +12 +9.5 6 3.5 0 -2.5 -6 -8.5 -12 -14.5 -18 -20.5 -24 -26.5 -30 Reserved REF_LEVEL (dB) Reserved -12 -12 -12 -12 -12 -12 -2.5 -6 -8.5 -12 -14.5 -18 -20.5 -24 -26.5 -30 Reserved 11110 1 11101 11100 11011 11010 11001 11000 10111 10110 < 10110 Note: 1 When the SVC is in Automatic mode (SVC_ON = 1), internal clipping may occur with a high reference level (REF_LEVEL = -2.5 or -6 dB). The maximum recommended value is -8.5 dB. 2 A mute of the corresponding audio output is recommended before switching ON/OFF. A gain discontinuity may create annoying audible plops. 67/95 Register List STV82x6 9.13 Surround LS_SRD_CTRL Loudspeaker Surround Control Register Address (hex): 5Bh Type: R/W Bit 7 SRD_ON Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 SRD_SEL Bit 1 SRD_STEREO Bit 0 STS_MODE Bit Name SRD_ON Reset 0 Surround Sound Enable 0: Surround Sound is disabled 1: Surround Sound is enabled Function Bits[6:3] SRD_SEL 0000 0 Reserved Surround Sound Select 0: ST WideSurround Sound (Default) 1: SRSTM Surround Sound. This option is only available if the SRS_ON bit in register CUT_ID is set. (STV8226/36 only) SRD_STEREO 0 Surround Sound Stereo Mode 0: Surround Sound in Mono mode (Default) 1: Surround Sound in Stereo mode STS_MODE 0 ST WideSurround Sound Mode Selection for Stereo Source Only The ST_ID bit in register AUTO_STAT must be set. 0: ST WideSurround Sound Movie mode (Default) 1: ST WideSurround Sound Music mode LS_STS_GAIN Address (hex): 5Ch Type: R/W Bit 7 Bit 6 Loudspeaker ST WideSurround Gain Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STS_GAIN[7:0] Bit Name STS_GAIN[7:0] Reset 10000000 Function Defines the ST WideSurround Sound component gain in linear scale. Level (%) 1000 0000 (Default) 0111 1111 0111 1110 0111 1101 ........ 100% 99.2% 98.4% 97.6% 0000 0100 0000 0011 0000 0010 0000 0001 0000 0000 Level (%) 3.1% 2.3% 1.6% 0.8% 0% 68/95 STV82x6 LS_STS_FREQ Address (hex): 5Dh Type: R Bit 7 0 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List Loudspeaker ST WideSurround Sound Frequency Bit 0 BASS_FREQ[1:0] MEDIUM_FREQ[1:0] TREBLE_FREQ[1:0] Bit Name Bits[7:6] BASS_FREQ[1:0] MEDIUM_FREQ[ 1:0] TREBLE_FREQ[ 1:0] Reset 00 01 01 01 Reserved. Function Defines the bass frequency effect for ST WideSurround Sound. Programmable values are listed in Table 24. Defines the medium frequency effect for ST WideSurround Sound in Movie or Mono mode (no effect in Music mode). Programmable values are listed in Table 24. Defines the treble frequency effect for ST WideSurround Sound in Movie or Mono mode (no effect in Music mode). Programmable values are listed in Table 24. Table 24: Phase Shifter Center Frequencies Phase Shifter Center Frequency BASS_FREQ[1:0] 00 01 (Default) 10 11 40 Hz 90 Hz 120 Hz 160 Hz MEDIUM_FREQ[1:0] 202 Hz 416 Hz 500 Hz 588 Hz TREBLE_FREQ[1:0] 2 kHz 4 kHz 5 kHz 6 kHz LS_SRS_SPACE Address (hex): 5Eh Type: R/W Bit 7 Bit 6 Loudspeaker SRSTM Surround Sound Space Effect Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRS_SPACE[7:0] Bit Name SRS_SPACE[7:0] Reset Function 10000000 Defines the gain of the SRSTM Surround component (in linear scale). Level (%) 1000 0000 (Default) 0111 1111 0111 1110 0111 1101 ........ 100% 99.2% 98.4% 97.6% 0000 0100 0000 0011 0000 0010 0000 0001 0000 0000 Level (%) 3.1% 2.3% 1.6% 0.8% 0% 69/95 Register List LS_SRS_CENTER Address (hex): 5Fh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x6 Loudspeaker SRSTM Surround Sound Center Effect Bit 0 SRS_CENTER[7:0] Bit Name SRS_CENTER [7:0] Reset 10000000 Function Defines the gain of the SRSTM Center component (in linear scale). Level (%) 1000 0000 (Default) 0111 1111 0111 1110 0111 1101 ........ 100% 99.2% 98.4% 97.6% 0000 0100 0000 0011 0000 0010 0000 0001 0000 0000 Level (%) 3.1% 2.3% 1.6% 0.8% 0% 9.14 5- Band Equalizer LS_EQ_CTRL Loudspeaker Equalizer Control Register Address (hex): 60h Type: R/W Bit 7 EQ_ON Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit Name EQ_ON Reset 0 5-Band Equalizer Enable 0: 5-Band Equalizer is disabled 1: 5-Band Equalizer is enabled (Default) Function Bits[6:0] 000000 Reserved. 70/95 STV82x6 LS_EQ_BAND[1:5] Address (hex): 61h to 65h Type: R/W Bit 7 0 0 0 0 0 Bit 6 0 0 0 0 0 Bit 5 0 0 0 0 0 Bit 4 Bit 3 Bit 2 EQ_BAND1_GAIN[4:0] (S) EQ_BAND2_GAIN[4:0] (S) EQ_BAND3_GAIN[4:0] (S) EQ_BAND4_GAIN[4:0] (S) EQ_BAND5_GAIN[4:0] (S) Bit 1 Register List Loudspeaker Equalizer Gain Bit 0 Bit Name Bits[7:5] Reset 000 Reserved. Function Band gain adjustment within a range from -12 dB to +12 dB in steps of 1 dB. EQ_BAND1_GAIN[4:0] EQ_BAND2_GAIN[4:0] EQ_BAND3_GAIN[4:0] EQ_BAND4_GAIN[4:0] EQ_BAND5_GAIN[4:0] 00000 00000 00000 00000 00000 BAND1 = BAND2 = BAND3 = BAND4 = BAND5 = Bass (Centered 100 Hz) Bass-Medium (Centered 330 Hz) Medium (Centered 1 kHz) Treble-Medium (Centered 3.3 kHz Treble (Centered 6.6 kHz) Table 25: Loudspeaker/Headphone Equalizer Gain Values Value 01100 01011 01010 ................ 00000 (Default) ................ 10110 10101 10100 Gain G (dB) +12 +11 +10 ..... 0 ..... -10 -11 -12 71/95 Register List STV82x6 9.15 Loudness/Bass & Treble LS_LOUD Loudspeaker Loudness Control Register Address (hex): 66h Type: R/W Bit 7 LOUD_ON Bit 6 Bit 5 LOUD_TH[2:0] Bit 4 Bit 3 LOUD_FREQ Bit 2 Bit 1 LOUD_GHR[2:0] Bit 0 Bit Name LOUD_ON Reset 0 Loudness Enable 0: Loudness disabled 1: Loudness enabled Function LOUD_TH[2:0] 000 Loudness Threshold Programmable values are listed in Table 26. LOUD_FREQ 0 Bass Cut-off Frequency Select 0: 40 Hz bass cut-off frequency (Normal mode) 1: 120 Hz bass cut-off frequency (Bass Amplified mode) LOUD_GHR[2:0] 010 Loudness Maximum Treble Gain Programmable values are listed in Table 26. Table 26: Loudness Control Values Bitfield Value 000 001 010 011 100 101 110 111 Threshold (dB) LOUD_TH[2:0] 0 (Default) -6 -12 -18 -24 -30 -36 -42 Max. Treble Gain (dB) LOUD_GHR[2:0] 0 3 6 (Default) 9 12 15 18 Reserved HP_BT_CTRL Address (hex): 71h Type: R/W Bit 7 BT_ON Bit 6 0 Headphone Bass/Treble Control Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 72/95 STV82x6 Register List Bit Name BT_ON Reset 0 Headphone Bass/Treble Enable 0: Headphone Bass/Treble disabled 1: Headphone Bass/Treble enabled Function Bit [6:0] 0 Reserved. HP_BASS_GAIN Address (hex): 72h Type: R/W Bit 7 0 Bit 6 0 Headphone Bass Gain Bit 5 0 Bit 4 Bit 3 Bit 2 BASS_GAIN[4:0] Bit 1 Bit 0 Bit Name Bits[7:5] BASS_GAIN[4:0] Reset 000 00000 Reserved Function Gain Tuning of Headphone Bass Frequency Gain may be programmed within a range between +12 dB and -12 dB in steps of 1 dB. Programmable values are listed in Table 25. HP_TREBLE_GAIN Address (hex): 73h Type: R/W Bit 7 0 Bit 6 0 Headphone Treble Gain Bit 5 0 Bit 4 Bit 3 Bit 2 TREBLE_GAIN[4:0] Bit 1 Bit 0 Bit Name Bits[7:5] TREBLE_GAIN [4:0] Reset 000 00000 Reserved Function Gain Tuning of Headphone Treble Frequency Gain may be programmed within a range between +12 dB and -12 dB in steps of 1 dB. Programmable values are listed in Table 25. 73/95 Register List STV82x6 9.16 Volume/Balance Control Registers LS_VOL_CTRL Loudspeaker Volume Control Register Address (hex): 67h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 BAL_MODE Bit Name Bits[7:1] BAL_MODE Reset 000000 Reserved. 1 0: Independent mode. 1: Differential mode (Default) Function HP_VOL_CTRL Address (hex): 75h Type: R/W Bit 7 0 Bit 6 0 Headphone Volume Control Register Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 BAL_MODE Bit Name Bits[7:1] BAL_MODE Reset 000000 Reserved. 1 0: Independent mode. 1: Differential mode (Default) Function LS_CVOL LS_VOL_L Address (hex): 68h Type: R/W Bit 7 Bit 6 Loudspeaker Common Volume Control Register Loudspeaker Left Volume Control Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CVOL[7:0] / VOL_L[7:0] Bit Name CVOL[7:0] Reset 00000000 Loudspeaker Common Volume Function Volume may be programmed within a range between 0 dB and -96 dB in steps of 0.375 dB. Programmable values are listed in Table 27. 74/95 STV82x6 Register List Bit Name VOL_L[7:0] Reset 00000000 Loudspeaker Left Volume Function Volume may be programmed within a range between 0 dB and -96 dB in steps of 0.375 dB. Programmable values are listed in Table 27. HP_CVOL HP_VOL_L Address (hex): 76h Type: R/W Bit 7 Bit 6 Headphone Common Volume Control Register Headphone Left Volume Control Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CVOL[7:0] / VOL_L[7:0] Bit Name CVOL[7:0] Reset 00000000 Headphone Common Volume Function Volume may be programmed within a range between 0 dB and -96 dB in steps of 0.375 dB. Programmable values are listed in Table 27. VOL_L[7:0] 00000000 Headphone Left Volume Volume may be programmed within a range between 0 dB and -96 dB in steps of 0.375 dB. Programmable values are listed in Table 27. Table 27: Common or Left Volume Control Values Register Value 1111 1111 1111 1110 1111 1101 ................ 1000 0000 (Default) ................ 0000 0010 0000 0001 0000 0000 Volume Level (dB) 0 (1 VRMS) -0.375 -0.75 ..... -48 ..... -94.50 -95.25 -95.625 75/95 Register List LS_BAL LS_VOL_R Address (hex): 69h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x6 Loudspeaker Balance Control Register Loudspeaker Right Volume Control Register Bit 0 BAL[7:0] / VOL_R[7:0] Bit Name BAL[7:0] Reset 00000000 Loudspeaker Differential Balance Function In Differential mode, the balance may be programmed in steps of 0.75 dB. Programmable values are listed in Table 28. VOL_R[7:0] 00000000 Loudspeaker Right Volume Control In Independent mode, the volume may be programmed within a range between 0 dB and -96 dB in steps of 0.375 dB. Programmable values are listed in Table 29. HP_BAL HP_VOL_R Address (hex): 77h Type: R/W Bit 7 Bit 6 Headphone Balance Control Register Headphone Right Volume Control Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BAL[7:0] / VOL_R[7:0] Bit Name BAL[7:0] Reset 00000000 Headphone Differential Balance Function In Differential mode, the balance may be programmed in steps of 0.75 dB. Programmable values are listed in Table 28. VOL_R[7:0] 00000000 Headphone Right Volume Control In Independent mode, the volume may be programmed within a range between 0 dB and -96 dB in steps of 0.375 dB. Programmable values are listed in Table 29. Table 28: Differential Balance Control Values Register Value 0111 1111 (7Fh) 0111 1110 0111 1101 ................ 0000 0000 (Default) ................ Left/Common Level -95.25 dB -94.50 dB -93.75 dB ..... 0 dB ..... 100% 0.78% 0.56% 2.34% Right/Common Level 0 dB 0 dB 0 dB ..... 0 dB ..... 100% 100% 100% 100% 76/95 STV82x6 Table 28: Differential Balance Control Values Register Value 1000 0010 1000 0001 1000 0000 (80h) Register List Left/Common Level 0 dB 0 dB 0 dB 100% 100% 100% Right/Common Level -94.50 dB -95.25 dB -96.00 dB 1.56% 0.78% 0.00% Table 29: Right/Left Volume Control Values Register Value 1111 1111 1111 1110 1111 1101 ................ 1000 0000 (Default) ................ 0000 0010 0000 0001 0000 0000 Volume Level (dB) 0 (1 VRMS) -0.375 -0.75 ..... -48 ..... -94.50 -95.25 -95.625 9.17 Subwoofer SW_GAIN Subwoofer Gain Address (hex): 6Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SW_GAIN[7:0] Bit Name SW_GAIN[7:0] Reset 10000000 Subwoofer Gain Function Gain may be programmed within a range between 0 dB and -96 dB in steps of 0.375 dB. Programmable values are listed in Table 27. 77/95 Register List SW_BAND Address (hex): 6Bh Type: R/W Bit 7 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 SW_FREQ[2:0] STV82x6 Subwoofer Bandwidth Control Bit 0 Bit Name Bits[7:3] SW_FREQ[2:0] Reset 00000 011 Reserved. Function Cut-off frequency tuning from 50 Hz to 400 Hz in steps of 50 Hz 000: 50 Hz 001: 100 Hz 010: 150 Hz 011: 200 Hz (Default) 100: 250 Hz 101: 300 Hz 110: 350 Hz 111: 400 Hz 9.18 Beeper BEEPER_CTRL Beeper Control Address (hex): 79h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 LS_BEEP_ON HP_BEEP_ON BEEP_MODE BEEP_DURATION[1:0] Bit Name LS_BEEP_ON Reset 0 Loudspeaker Beeper Enable Function 0: Loudspeaker beeper muted (Default) 1: Loudspeaker beeper enabled (Start pulse and automatic reset in Pulse mode) HP_BEEP_ON 0 Headphone Beeper Enable 0: Headphone beeper muted (Default) 1: Headphone beeper enabled (Start pulse and automatic reset in Pulse mode) BEEP_MODE 0 Beeper Mode Select 0: Pulse mode (for Beep applications - Default) 1: Continuous mode (for Alarm application)s Bit[4:0] BEEP_DURATION[ 1:0] 000 00 Reserved. Defines the duration of the beeper (for Pulse mode only). 00: 0.128 01: 0.256 10: 0.512 11: 1.024 s s. s. s. 78/95 STV82x6 BEEPER_TONE Address (hex): 7Ah Type: R/W Bit 7 Bit 6 BEEP_FREQ[2:0] Bit 5 Bit 4 Bit 3 Bit 2 BEEP_VOL[4:0] Bit 1 Register List Beeper Tone Control Bit 0 Bit Name BEEP_FREQ[2:0] Reset 011 Function Defines the frequency of the beeper tone from 62.5 Hz to 8 kHz in octaves 000: 62.5 Hz 001: 125 Hz 010: 250 Hz 011: 500 Hz (Default) 100: 1 kHz 101: 2 kHz 110: 4 kHz 111: 8 kHz BEEP_VOL[4:0] 10000 Defines the Beeper volume from 0 to -93 dB in steps of 3 dB. 11111: 0 dB (1 VRMS) 11110: -3 dB 11101: -6 dB ... 10000: -48 dB (Default) ... 00011: -84 00010: -87 00001: -90 00000: -93 dB dB dB dB 79/95 Input/Output Groups STV82x6 10 Input/Output Groups Pin numbers applyto SDIP package only. VDDH VDDH VDDA 400 SIF 1 5K VREFIF MONOIN 6 22K VREFIF GNDIF GNDIF VDDH VDDIF VDDH VDDH 2K 160 VTOP 2 AO1L AO1R AO2L AO2R 500 7 8 19 20 300 GNDIF GNDA GNDA VDDH VDDH VDDH BGAP(1.2V) 2K VREFIF 3 6K LSL LSR SW HPL HPR 26 27 28 29 30 30K GNDIF GNDA GNDA 80/95 STV82x6 Input/Output Groups VDDH VDDH 40K BGAP (1.2V) 82K AI1L AI1R AI2L AI2R AI3L AI3R 11 12 15 16 23 24 90K VREFA 22 3K 47K 15K GNDA GNDA GNDA VDDH VDDH 200 BGAP (1.2V) 10K VMC1 13 6K BGAP 25 BAND-GAP=1.2V 30K GNDA GNDA VDDH BGAP (1.2V) VDDC 9 VMC2 14 6K 76 BGAP (1.2V) 30K GNDA GNDA 81/95 Input/Output Groups STV82x6 VDDH 21 VDDA 17 VDDC 9 VDDIF 4 GNDS 31 GNDC 10 GNDIF 5 GNDA 18 GND1 HPD 32 ADR 33 RESET 37 VDD2 VDDA 17 76 BGAP (1.2V) SDO ST WS SCK BUS1 BUS0 IRQ 50 51 52 53 54 55 56 6 GNDA 18 GND2 REG 36 8K 1.2K BGAP (1.2V) VDD1 VDD1 40 VDD2 48 MCK 39 6 GND1 41 GND2 47 GND1 82/95 STV82x6 Input/Output Groups VDD1 SYSCK 38 3 GND1 SCL SDA 34 35 12 GND1 VDDP XTI 43 GNDP XTO 44 83/95 Electrical Characteristics STV82x6 11 Electrical Characteristics A 10 kW load is applied to all outputs. 11.1 Absolute Maximum Ratings Parameter Digital Supply Voltage (VDD1, V DD2, VDDP) Analog Supply High Voltage (VDDH) Capacitor 100 pF discharged via 1.5 kW serial resistor (Human Body Model) Operating Ambient Temperature Storage Temperature Symbol DVDD HVDD VESD TOPER TSTG Value 4.6 9.5 4 0, +70 -55 to +150 Units V V kV C C Note: Analog supply voltages (VDDIF, VDDC and VDDA) are regulated by internal circuits. For more information, refer to Section 7.1: Supply Voltages. 11.2 Thermal Data Parameter Junction-to-Ambient Thermal Resistance SDIP56 TQFP80 Symbol RthJA Value 40 42 Units C/W 11.3 Supply Test Conditions: TOPER = 25 C, VDDH = 8 V, VDDA is supplied by 8 V via 330 W, VDDIF is connected to VDDC and is supplied by 5 V via 22 W and DVDD (VDD1, VDD2 and VDDP) is supplied by 5 V via an external ballast transistor. For more information, refer to Figure 4 on page 6. Symbol DV DD HVDD AV DD IVDD IVDDIF IVDDC IVDDA IVDDH Parameter Digital Supply Voltage (VDD1, V DD2, VDDP) Analog Supply High Voltage (VDDH) Analog Supply Voltage (VDDIF, VDDC, VDDA) VDD Current Consumption (VDD1, VDD2, VDDP) VDDIF Current Consumption (VDDIF, VDDC) VDDA Current Consumption Test Conditions Min. 3.0 7.6 3.0 130 60 7 Typ. 3.3 8.0 3.3 160 75 12 15 Max. 3.6 8.4 3.6 190 85 18 Units V V V mA mA mA mA 5.0 V VDDH Current Consumption 8.0 V 15 25 35 84/95 STV82x6 Electrical Characteristics 11.4 Crystal Recommendations Parameter Crystal Parallel Resonance Frequency (at 22 pF load capacitor) Frequency Tolerance at 25 C Frequency Stability versus Temperature within a range from 0 to 70 C Motional Capacitor Serial Resistance Shunt Capacitance -50 -50 8 50 7 Symbol FP DF/F P DF/FT C1 RS CS Min. Typ. 27 Max. Units MHz +50 +50 ppm ppm fF W pF 11.5 Analog Sound IF Signal Recommendations Parameter SIF Carrier Frequency SIF Input Resistance SIF Input DC Level SIF Input Capacitance Symbol FSIF RINSIF DCINSIF CINSIF FM Carrier VSIFFM DEVFM Test Conditions Min. 4 4.5 Typ. Max. 8 Units MHz kW V 6 1.47 7.5 15 pF SIF Input Level for FM Carrier FM Deviation FM50k (Standard) FM200k (DK only) FM350k (DK only) FM500k (DK mono only) 0.02 15 50 200 1.6 125 VPP kHz 350 500 1 5 120 7 13 kHz kHz dB dB DFSIF FM SIF Carrier Accuracy for FM Standard (FM50k) Shifted Standard (FM50k with DCO compensation) RFM1/FM2 RFM/QPSK AM Carrier VSIFAM DEVAM DFSIFAM RAM/QPSK Carrier Ratio FM1/FM2 for A2 System Carrier Ratio FM/QPSK for NICAM System SIF Input Level for AM Carrier (Unmodulated) Modulation Depth for AM SIF Carrier Accuracy for AM AM/QPSK Carrier Ratio for NICAM System 0.04 0 1 17 0.8 100 5 VPP % kHz dB 85/95 Electrical Characteristics STV82x6 11.6 SIF to LS/HP/SCART Path Characteristics Parameter Test Conditions Min. Typ. Max. Units Symbol FM Demodulation BANDFM SNRFM THDFM Frequency Response Signal to Noise Total Harmonic Distortion 20Hz - 15kHz RMS unweighted, 20Hz-15kHz, Standard B/G 50 kHz FM Deviation,1kHz LS Output 0.7 VRMS RMS -1.5 70 +1.5 dB dB 0.1 % SEPFM Stereo Channel Separation Standard B/G stereo A2, 50 kHz FM deviation, 1 kHz RMS 45 dB XTALKFM Dual Channel Crosstalk Standard B/G dual mono A2, 50 kHz FM deviation, 1 kHz 80 dB NICAM Demodulation BANDNIC SNR NIC THDNIC SEPNIC XTALKNIC Frequency Response Signal to Noise Total Harmonic Distortion Stereo Channel Separation Dual Channel Crosstalk 20Hz - 15kHz RMS unweighted, 20Hz-15kHz, Standard B/G mono NICAM,1 kHz LS Output 0.7 VRMS RMS Standard B/G stereo NICAM, 1 kHz RMS Standard B/G dual mono NICAM, 1 kHz -1.0 72 0.1 80 80 +1.0 dB dB % dB dB AM Demodulation BANDAM SNRAM THDAM Frequency Response Signal to Noise Total Harmonic Distortion 20 Hz - 15 kHz RMS unweighted 2 0Hz-15 kHz, Standard L, 54% AM Depth, 1 kHz LS Output 0.7 VRMS -1.0 50 0.6 +1.0 dB dB % 11.7 SCART to SCART Analog Path Characteristics Parameter Test Conditions Min. Typ. Max. Units Symbol Analog-to-Analog (Through mode) RINSCART ROUTSCART SCART Input Resistance Output Resistance for SCARTs 24 250 30 300 2.55 VDDH = 5 V VDDH = 8 V VIN = 2 VRMS at 1 kHz for VDDH = 8 V VIN = 1.00 VRMS at 1 kHz for VDDH = 5 V VIN = 1.75 VRMS at 1 kHz for VDDH = 8 V 2.20 3.40 0.1 0.0125 0.0125 0.5 0.03 0.05 40 450 kW W V V % % VDCINSCART SCART Input DC Level VDCOUTSCART SCART Output DC Level Clipping THD THD Total Harmonic Distortion 86/95 STV82x6 Electrical Characteristics Symbol Parameter Test Conditions 20 to 20 kHz Bandwidth, RMS unweighted VIN = 1.00 V RMS for VDDH = 5 V VIN = 1.75 V RMS for VDDH = 8 V 20 Hz to 20 kHz 1.4 VRMS @ 1 kHz on ref signal, the other one grounded 1.4 VRMS @ 1 kHz on ref signal, all other inputs grounded 1.4 VRMS @ 1 kHz on reference output, signal on a single input, all other inputs grounded Min. Typ. Max. Units SNR Signal to Noise Ratio 75 80 -0.5 70 85 90 0.5 75 dB BAND XTALKL/R XTALKIN1/2 Frequency Response Left/Right Crosstalk Audio Crosstalk from Input Channel 1 to Input Channel 2 Audio Crosstalk from Output Channel 1 to Output Channel 2 dB dB 80 85 dB XTALKOUT1/2 80 85 dB 11.8 SCART to I2S Output Path (via ADC) Characteristics Parameter THD Symbol Clipping Test Conditions VIN = 1 VRMS at 1 kHz for VDDH = 5 V VIN = 2 VRMS at 1 kHz for VDDH = 8 V VIN = 0.90 VRMS at 1 kHz for VDDH = 5 V VIN = 1.75 VRMS at 1 kHz for VDDH = 8 V 20 to 15 kHz Bandwidth, RMS unweighted VIN = 0.90 V RMS for VDDH = 5 V VIN = 1.75 V RMS for VDDH = 8 V 20 Hz to 15 kHz Min. Typ. 0.5 0.2 0.03 0.03 Max. 2.0 2.0 0.05 0.05 Units % THD Total Harmonic Distortion % SNR Signal to Noise Ratio 70 70 -0.5 74 74 0.5 dB BAND Frequency Response dB 11.9 MONOIN to ADC and I2S Output Path Characteristics Parameter MONO Input Resistance Symbol R INMONOIN Test Conditions Min. 15 Typ. 22 1.45 Max. 30 Units kW V VDC INMONOIN MONO Input DC Level THD SNR BAND Total Harmonic Distortion Signal to Noise Ratio Frequency Response VIN = 0.45 VRMS at 1 kHz 20 to 15 kHz Bandwidth, RMS unweighted VIN = 0.45 VRMS 20 Hz to 15 kHz 70 -0.5 0.03 74 0.05 % dB 0.5 dB 11.10 I2S to LS/HP/SW Path Characteristics Symbol ROUTMAIN Parameter Output Resistance for Main Outputs Test Conditions LSL, LSR, SW, HPL and HPR pins Min. Typ. 5 2.20 Max. 30 Units W V VDCOUTMAIN MAIN Output DC Level 87/95 Electrical Characteristics STV82x6 Symbol THD SNR VOUTAMP Parameter Total Harmonic Distortion Signal to Noise Ratio MAIN Output Amplitude Test Conditions 90% Full-scale Range at 1 kHz 20 to 15 kHz Bandwidth, RMSunweighted, 90% Full-scale Range 90% Full-scale Range at 1 kHz Min. Typ. 0.025 Max. 0.050 Units % dB 72 0.800 76 0.875 0.950 VRMS 11.11 I2S to SCART Path Characteristics Symbol THD SNR VOUTAMP Parameter Total Harmonic Distortion Signal to Noise Ratio MAIN Output Amplitude Test Conditions 90% Full-scale Range at 1 kHz 20 Hz to 15 kHz Bandwidth unweighted, 90% Full-scale Range 90% Full-scale Range at 1 kHz, VDDH = 8V Min. Typ. 0.025 Max. 0.100 Units % dB 72 1.60 76 1.75 1.90 VRMS 11.12 Loudspeaker and Headphone Volume Control Characteristics Symbol VOL_MIN VOL_DNL Parameter Maximum Attenuation Maximum Non-Linearity Step to Step Test Conditions I2S to DAC at 1 kHz with 1 active channel Volume Control Range of 0 dB to 72 dB Min. 82 Typ. 90 0.1 Max. Units dB 0.3 dB 11.13 MUTE Performance Symbol DAC Mute SCART Mute Parameter Test Conditions I2S to DAC at 1 kHz with 1 active channel 1.4 VRMS @ 1 kHz on ref signal, all other inputs grounded Min. 85 78 Typ. 95 81 Max. Units 11.14 Digital I/Os Symbol V V IL Parameter Low Level Input Voltage High Level Input Voltage Input Current Test Conditions Min. Typ. Max. 0.5 Units V V IH 2.0 1 IIN mA 88/95 STV82x6 Electrical Characteristics 11.15 IC Bus Interface Symbol SCL VIL VIH VOL fSCL tr, tf II(L) Cl SDA VIL VIH tr, tf II(L) VOL tfo CL IACK TIMING tLOW tHIGH tSU, DAT tHD, DAT tSU, STOP tBUF tHD, STA tSU, STA Low Period High Period Data Setup Time Data Hold Time Stop Setup Time from Clock High Start Setup Time following a Stop Start Hold Time Start Setup Time following Clock Low to High Transition 1 1 250 250 1 1 1 1 ms ms ns ns ms ms ms ms Input Voltage Low Level Input Voltage High Level Input Rise/Fall Times (10 to 90%) Input Leakage Current (VI = 5.5 V with Output Off) Low Output Voltage (IOL = 3 mA) Output Fall Time between 3 V and 1 V Load Capacitance Maximum Sink Current 0 0 3 0.7 VDD 0.8 10 0.8 0.6 400 3 V V ms mA V s pF mA Input Voltage Low Level Input Voltage High Level Low Output Voltage (IOL = 3 mA) SCL Clock Frequency Input Rise/Fall Times (10 to 90%) Input Leakage Current (VI = 5.5 V) Input Capacitance 0 3 0 0.7 VDD 0.8 400 0.8 10 10 V V V kHz ms mA pF Parameter Min. Typ. Max. Units 89/95 Electrical Characteristics Figure 18: Serial Bus Timing tbuf SDA thd, sta SCL SDA for Start and Stop tr tlow thd, dat thigh tsu, dat tf STV82x6 tsu, sta tsu, sto 90/95 STV82x6 Package Mechanical Data 12 Package Mechanical Data Figure 19: 56-Pin Shrink Plastic Dual In Line Package, 600-mil Width SDIP56 mm Dim. inches A A1 A2 b b2 C D E E1 e eA eB L 2.92 12.32 1.78 15.24 0.20 50.29 15.01 0.38 3.18 0.41 0.89 6.35 0.015 4.95 0.125 0.016 0.035 0.38 53.21 0.008 1.980 0.591 14.73 0.485 0.070 0.600 17.78 5.08 0.115 0.250 0.195 0.015 2.095 0.580 0.700 0.200 91/95 Package Mechanical Data Figure 20: 80-Pin Thin Plastic Quad Flat Package STV82x6 D D1 A1 A A2 b e E1 E L1 L h c mm Dim. Min. A A1 A2 b C D D1 E E1 e K L L1 0 0.45 0.05 1.35 0.22 0.09 16.00 14.00 16.00 14.00 0.65 3.5 0.60 1.00 0.75 0.75 0 0.018 1.40 0.32 inches Max. 1.60 0.15 1.45 0.38 0.20 0.002 0.053 0.009 0.004 0.630 0.551 0.630 0.551 0.026 3.5 0.024 0.039 0.75 0.030 0.055 0.013 Typ. Min. Typ. Max. 0.063 0.006 0.057 0.015 0.008 92/95 STV82x6 Revision History 13 Revision History Modification DATA SHEET First Issue Modification to Table 6: Volume/Balance Control Registers on page 19. Addition of pin 12 (TQFP80) to Table 2. Updated Figure 5. Revision 2.0 2.1 2.2 Date January 2003 May 2003 May 2004 93/95 STV82x6 Index A Analog Power Supply ........................................ 27 Analog-to-Digital Conversion ............................. 10 Automatic Frequency Control ............................ 12 Automatic Gain Control ...................................... 10 Automatic Overmodulation Detection ................ 11 Automatic Standard Recognition System 10-11, 31 M Mute Control ...................................................... 19 O Output Audio Matrixing ...................................... 24 B Balance Control ................................................. 18 Bass Control ...................................................... 17 Beeper ............................................................... 20 P Peak Detector .................................................... 11 Peak Level Detector .......................................... 24 Philips Mode ...................................................... 26 Power Supplies .................................................. 27 C Clock .................................................................. 14 Clock System Output ......................................... 26 S Signal to Noise ................................................... 86 Smart Volume Control ....................................... 16 Sony Mode ......................................................... 26 Sound IF Signal ................................................. 10 SRS 3D Surround .............................................. 21 ST Wide Surround ............................................. 17 Stereo Flag ........................................................ 25 Supply Voltages ................................................. 27 D Digital Power Supply .......................................... 27 Digital Stereo Output ......................................... 26 H T Headphone Detection Mode .............................. 19 Total Harmonic Distortion .................................. 86 Treble Control .................................................... 17 I I2C Address ....................................................... 29 I2S ..................................................................... 26 Independent Mute Control ................................. 19 Input Audio Matrixing ......................................... 24 V Voltage Regulator .............................................. 27 Volume Control .................................................. 18 L Loudness Control .............................................. 20 W Word Selection Polarity ..................................... 26 94/95 STV82x6 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com The SoundRetrieval System and are registered trademarks of SRS Labs, Inc. 95/95 |
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